公开(公告)号：US20190058082A1

公开(公告)日：2019-02-21

申请号：US15678385

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak K. NAYAK ,  Srinivasa R. BANNA ,  Ajey P. JACOB

IPC: H01L33/00 ,  H01L33/06 ,  H01L33/08 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture. The structure includes a buffer layer; at least one dielectric layer on the buffer layer, the at least one dielectric layer having a plurality of openings exposing the buffer layer; and a plurality of uniformly sized and shaped nanowires or nanosheets formed in the openings and extending above the at least one dielectric layer.

公开(公告)号：US20190013436A1

公开(公告)日：2019-01-10

申请号：US15643061

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak K. NAYAK ,  Srinivasa R. BANNA ,  Ajey P. JACOB

IPC: H01L33/12 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/22

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.

公开(公告)号：US20190006413A1

公开(公告)日：2019-01-03

申请号：US15635608

申请日：2017-06-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. JACOB ,  Deepak K. NAYAK ,  Srinivasa R. BANNA

IPC: H01L27/15 ,  H01L29/08 ,  H01L29/78 ,  H01L33/32 ,  H01L29/16 ,  H01L29/417 ,  H01L33/36 ,  H01L29/778 ,  H01L33/00 ,  H01L29/66 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L27/15 ,  H01L25/167 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7827 ,  H01L29/872 ,  H01L33/007 ,  H01L33/32 ,  H01L33/36 ,  H01L33/38 ,  H01L2933/0016

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.

公开(公告)号：US20180012812A1

公开(公告)日：2018-01-11

申请号：US15667305

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar PATIL ,  Ajey P. JACOB

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L21/823885 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02653 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US20170092373A1

公开(公告)日：2017-03-30

申请号：US14867331

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Min-hwa CHI ,  Ajey P. JACOB

IPC: G11C17/16 ,  H01L29/06 ,  H01L23/525 ,  H01L29/78

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L29/0673 ,  H01L29/785

Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

公开(公告)号：US20150024572A1

公开(公告)日：2015-01-22

申请号：US13945445

申请日：2013-07-18

Applicant: INTERNATIONAL BUSINESS MACHIES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Kangguo CHENG ,  Bruce B. DORIS ,  Nicolas LOUBET ,  Prasanna KHARE ,  Ramachandra DIVAKARUNI

IPC: H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了半导体制造方法，其包括：通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。

公开(公告)号：US20190296160A1

公开(公告)日：2019-09-26

申请号：US16438863

申请日：2019-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. JACOB

IPC: H01L31/0232 ,  H01L31/0392 ,  H01L27/144 ,  G02B6/12 ,  H01L31/18 ,  H01L31/0352 ,  H01L31/105

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.

公开(公告)号：US20180301569A1

公开(公告)日：2018-10-18

申请号：US15486849

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. JACOB

IPC: H01L31/0232 ,  H01L31/105 ,  H01L31/18 ,  H01L31/028 ,  H01L31/0352 ,  G02B6/122

CPC classification number: H01L31/02327 ,  G02B6/12004 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12123 ,  H01L27/144 ,  H01L27/1446 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/105 ,  H01L31/1804

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.

公开(公告)号：US20180033726A1

公开(公告)日：2018-02-01

申请号：US15724563

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Suraj K. PATIL ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US20170338277A1

公开(公告)日：2017-11-23

申请号：US15599458

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srinivasa BANNA ,  Deepak NAYAK ,  Ajey P. JACOB

IPC: H01L27/15 ,  H01L33/62 ,  H01L33/06 ,  H01L33/20 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16 ,  H01L33/32

CPC classification number: H01L27/156 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/06 ,  H01L33/12 ,  H01L33/16 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1−xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1−xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1−xN layer in the red LED, the green LED and the blue LED.