公开(公告)号：US20180342427A1

公开(公告)日：2018-11-29

申请号：US15602225

申请日：2017-05-23

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Hui Zang ,  Guowei Xu

IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L21/823878 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

公开(公告)号：US20180286956A1

公开(公告)日：2018-10-04

申请号：US15477565

申请日：2017-04-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

CPC分类号： H01L29/41775 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66545

摘要： One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US20180277645A1

公开(公告)日：2018-09-27

申请号：US15470205

申请日：2017-03-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/417

摘要： Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. A second dielectric layer is formed on the first metal gate electrode, the second metal gate electrode, and the first dielectric layer. An opening is formed in the second dielectric layer that extends in a vertical direction to expose a section of the first metal gate electrode. The section of the first metal gate electrode is removed, while the second metal gate electrode is masked by the second dielectric layer, to define a gate cut at a location of the opening. The gate cut may be subsequently filled by dielectric material.

公开(公告)号：US20180261514A1

公开(公告)日：2018-09-13

申请号：US15455203

申请日：2017-03-10

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Laertis Economikos ,  Chanro Park ,  Min Gyu Sung

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823828 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed are method embodiments for forming an integrated circuit (IC) structure with at least one first-type FINFET and at least one second-type FINFET, wherein the first-type FINFET has a first replacement metal gate (RMG) adjacent to a first semiconductor fin, the second-type FINFET has a second RMG adjacent to a second semiconductor fin, and the first RMG is in end-to-end alignment with the second RMG and physically and electrically isolated from the second RMG by a dielectric column. The method embodiments minimize the risk of the occurrence defects within the RMGs by forming the dielectric column during formation of the first and second RMGs and, particularly, after deposition and anneal of a gate dielectric layer for the first and second RMGs, but before deposition of at least one of multiple work function metal layers. Also disclosed herein are IC structure embodiments formed according to the above-described method embodiments.

公开(公告)号：US10008577B2

公开(公告)日：2018-06-26

申请号：US15225152

申请日：2016-08-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC分类号： H01L27/00 ,  H01L21/00 ,  H01L29/49 ,  H01L23/535 ,  H01L29/06 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L29/4991 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.

公开(公告)号：US10002932B2

公开(公告)日：2018-06-19

申请号：US15345137

申请日：2016-11-07

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim ,  Chanro Park

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L29/41791 ,  H01L21/0332 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/665

摘要： A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US09984919B1

公开(公告)日：2018-05-29

申请号：US15664584

申请日：2017-07-31

申请人： GLOBALFOUNDRIES Inc.

发明人： Xunyuan Zhang ,  Chanro Park ,  Yongan Xu ,  Peng Xu ,  Yann Mignot

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53295

摘要： Interconnect structures and methods of fabricating an interconnect structure. A first section of a mandrel is covered with a feature of an etch mask. A top surface of a second section of the mandrel is exposed by the feature of the etch mask and is recessed with an etching process. A conductive via is formed that reproduces a shape of the first section of the mandrel, and a conductive line is formed that reproduces a shape of the second section of the mandrel. The mandrel is removed to release the conductive via and the conductive line.

公开(公告)号：US20180130895A1

公开(公告)日：2018-05-10

申请号：US15345644

申请日：2016-11-08

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC分类号： H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC分类号： H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

摘要： One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US09859125B2

公开(公告)日：2018-01-02

申请号：US15072626

申请日：2016-03-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Kwan-Yong Lim

IPC分类号： H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11 ,  H01L29/06 ,  H01L29/161

CPC分类号： H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

摘要： Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US09685522B1

公开(公告)日：2017-06-20

申请号：US15093952

申请日：2016-04-08

申请人： GLOBALFOUNDRIES Inc.

发明人： Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie ,  Chanro Park

IPC分类号： H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L29/42392 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/775

摘要： Methods for forming uniform WF metal layers in gate areas of NS structures in a NS FET and the resulting devices are disclosed. Embodiments include providing NS structures, parallel to and spaced from each other, in a substrate; conformally forming gate dielectric and metal layers, respectively, on all surfaces in a gate area of each NS structure; forming a barrier layer on surfaces in the gate area of each NS structure except on surfaces in between the NS structures by PVD or PECVD; annealing the NS structures including the gate dielectric and metal layers; removing the barrier and metal layers from all surfaces; and forming a WF metal layer on all surfaces in the gate area of each NS structure.