公开(公告)号：US09147696B2

公开(公告)日：2015-09-29

申请号：US14043243

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Andy Wei ,  Lun Zhao ,  Dae Geun Yang ,  Jin Ping Liu ,  Tien-Ying Luo ,  Guillaume Bouche ,  Mariappan Hariharaputhiran ,  Churamani Gaire

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

公开(公告)号：US10020383B2

公开(公告)日：2018-07-10

申请号：US14716938

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jer-Hueih(James) Chen ,  Cuiqin Xu ,  Padmaja Nagaiah

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/28008 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

公开(公告)号：US09490340B2

公开(公告)日：2016-11-08

申请号：US14308138

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L29/6653 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract translation: 形成纳米线器件的方法包括图案化多个半导体材料层，使得每个层具有第一和第二暴露的端表面。 该方法还包括在半导体材料层的第一和第二暴露的端表面中形成掺杂的延伸区域。 该方法还包括：在形成掺杂的延伸区域之后，在器件的源极和漏极区域中形成外延半导体材料。

公开(公告)号：US20150372111A1

公开(公告)日：2015-12-24

申请号：US14308257

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L29/66 ,  H01L29/76

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/775

Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Abstract translation: 形成纳米线器件的方法包括在半导体衬底之上形成半导体材料层，在半导体材料层之上形成栅极结构，形成与栅极结构相邻的第一侧壁间隔物，并形成邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括使半导体材料层图案化，使得每个层具有第一和第二暴露的端表面。 栅极结构，第一侧壁间隔件和第二侧壁间隔件在图案化工艺期间被组合用作蚀刻掩模。 该方法还包括去除第一和第二侧壁间隔物，从而暴露图案化的半导体材料层的至少一部分。 该方法还包括在除去第一和第二侧壁间隔物之后，在至少图案化的半导体材料层的暴露部分中形成掺杂的延伸区域。

公开(公告)号：US09129987B2

公开(公告)日：2015-09-08

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jin Ping Liu ,  Guillaume Bouche ,  Andy Wei ,  Lakshmanan H. Vanamurthy ,  Cuiqin Xu ,  Sridhar Kuchibhatla ,  Rama Kambhampati ,  Xiuyu Cai

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧上沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US20150214345A1

公开(公告)日：2015-07-30

申请号：US14164368

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jinping Liu ,  Churamani Gaire ,  Mariappan Hariharaputhiran ,  Andy Chih-Hung Wei ,  Bharat V. Krishnan ,  Cuiqin Xu ,  Michael Ganz

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/88 ,  H01L29/73 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66151 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7311 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/88

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.

Abstract translation: 提供了用于在集成电路（IC）器件（例如，金属氧化物半导体场效应晶体管（MOSFET））中隔离源极和漏极区域的方法。 具体地，该器件包括形成在衬底上的栅极结构，与栅极结构相邻嵌入在衬底内的源极和漏极（S / D）以及S / D和衬底之间的衬里层（例如，硅 - 碳） 。 在一种方法中，衬垫层也形成在S / D的顶部。 因此，形成在接合部中的衬垫层防止掺杂剂从源极/漏极扩散。

公开(公告)号：US09390979B2

公开(公告)日：2016-07-12

申请号：US14482529

申请日：2014-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Huy M. Cao ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823437 ,  H01L27/088

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成一组掩模。 这组掩模中的每个掩模覆盖至少一个源/漏（s / d）接触位置。 从半导体结构的未被该组掩模覆盖的其余部分去除氧化物层。 然后在除去氧化物层的剩余部分中形成相对掩模填充层。 然后从半导体结构的其余部分去除氧化物层，即，先前被该组掩模和触点覆盖的部分形成在通过去除其余部分形成的凹部中的至少s / d接触位置 氧化层。

公开(公告)号：US09306019B2

公开(公告)日：2016-04-05

申请号：US14457934

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jing Wan ,  Guillaume Bouche ,  Andy Wei ,  Shao Ming Koh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract translation: 提供了集成电路及其制造方法。 一种集成电路的制造方法，其特征在于，形成覆盖基板的分层散热片，其中层状散热片包括SiGe层和Si层。 SiGe层和Si层沿着层状翅片的高度交替。 形成覆盖基板和分层翅片的虚拟栅极以及与层状翅片接触形成的源极和漏极区域。 去除伪栅极以暴露SiGe层和Si层，并且去除Si层以产生SiGe纳米线。 形成在源极和漏极之间封装SiGe纳米线的高K电介质层，并且形成替代金属栅极，使得替代金属栅极包围源极和漏极之间的高K电介质层和SiGe纳米线。

公开(公告)号：US20150372115A1

公开(公告)日：2015-12-24

申请号：US14308138

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/6653 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract translation: 形成纳米线器件的方法包括图案化多个半导体材料层，使得每个层具有第一和第二暴露的端表面。 该方法还包括在半导体材料层的第一和第二暴露的端表面中形成掺杂的延伸区域。 该方法还包括：在形成掺杂的延伸区域之后，在器件的源极和漏极区域中形成外延半导体材料。

公开(公告)号：US20150333162A1

公开(公告)日：2015-11-19

申请号：US14279495

申请日：2014-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jing Wan ,  Andy C. Wei ,  Shao-Ming Koh

IPC: H01L29/775 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/28512 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/78696

Abstract: A device includes a gate structure and a nanowire channel structure positioned under the gate structure. The nanowire channel structure includes first and second end surfaces. The device further includes a first insulating liner positioned on the first end surface and a second insulating liner positioned on the second end surface. The device further includes a metal-containing source contact positioned on the first insulating liner and a metal-containing drain contact positioned on the second insulating liner.

Abstract translation: 一种器件包括位于栅极结构下方的栅极结构和纳米线沟道结构。 纳米线通道结构包括第一和第二端面。 该装置还包括位于第一端表面上的第一绝缘衬垫和位于第二端表面上的第二绝缘衬垫。 该装置还包括定位在第一绝缘衬垫上的含金属源触点和位于第二绝缘衬垫上的含金属的漏极触点。