公开(公告)号：US09790086B2

公开(公告)日：2017-10-17

申请号：US15268244

申请日：2016-09-16

Applicant: Infineon Technologies AG

Inventor： Franz-Peter Kalz ,  Horst Theuss ,  Bernhard Winkler ,  Khalil Hosseini ,  Joachim Mahler ,  Manfred Mengel

IPC: G01B7/16 ,  B81B7/02 ,  G01L9/00 ,  G01L19/02 ,  G01L19/00 ,  B81B3/00 ,  G01L1/18

CPC classification number: B81B7/02 ,  B81B3/0021 ,  B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C2203/0154 ,  G01L1/18 ,  G01L9/0072 ,  G01L19/0092 ,  G01L19/02

Abstract: A micromechanical semiconductor sensing device is disclosed. In an embodiment the sensing device includes a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, the piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.

公开(公告)号：US09633927B2

公开(公告)日：2017-04-25

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

公开(公告)号：US09496228B2

公开(公告)日：2016-11-15

申请号：US14987820

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler ,  Ivan Nikitin

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (CTE) value of the electrically conductive composite material may be lower than the CTE value of the metal.

Abstract translation: 在各种实施例中，提供集成电路。 集成电路可以包括固定到半导体芯片的半导体芯片和导电复合材料，其中导电复合材料可以包括金属，并且其中导电复合材料的热膨胀系数（CTE）值可以是 低于金属的CTE值。

公开(公告)号：US20160043054A1

公开(公告)日：2016-02-11

申请号：US14451868

申请日：2014-08-05

Applicant: Infineon Technologies AG

Inventor： Rupert Fischer ,  Peter Strobel ,  Joachim Mahler ,  Konrad Roesl ,  Alexander Heinrich

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49575 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/04026 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8381 ,  H01L2224/8382 ,  H01L2224/83851 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95091 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00

Abstract: Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

Abstract translation: 公开了将芯片连接到芯片载体的方法。 在一些实施例中，用于将多个芯片连接到芯片载体的方法包括将第一芯片放置在转移载体上，将第二芯片放置在转移载体上，将具有第一和第二芯片的转移载体放置在芯片载体上并形成 第一芯片和芯片载体以及第二芯片和芯片载体。

公开(公告)号：US20150279782A1

公开(公告)日：2015-10-01

申请号：US14735604

申请日：2015-06-10

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

IPC: H01L23/538 ,  H01L23/495 ,  H01L21/288 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/4821 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/00 ,  H05K3/4661

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

公开(公告)号：US20140138843A1

公开(公告)日：2014-05-22

申请号：US13681079

申请日：2012-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L23/538 ,  H01L21/58 ,  H01L21/78

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US20140138841A1

公开(公告)日：2014-05-22

申请号：US13678675

申请日：2012-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3171 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side.

Abstract translation: 提供一种集成电路，所述集成电路包括：具有第一芯片侧和与所述第一芯片侧相对的第二芯片侧的芯片，所述芯片在所述第二芯片侧具有至少一个接触区域; 封装材料至少部分覆盖芯片; 以及至少一个接触通孔，其包括与所述至少一个接触区域接触并延伸穿过所述封装材料并通过所述芯片在所述第一芯片侧和所述第二芯片侧之间的导电材料。

公开(公告)号：US11296015B2

公开(公告)日：2022-04-05

申请号：US17036271

申请日：2020-09-29

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Giovanni Ragasa Garbin ,  Chen Wen Lee ,  Benjamin Reichert ,  Peter Strobel

IPC: H01L29/40 ,  H01L21/00 ,  H01L23/495 ,  H01L23/00

Abstract: A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

公开(公告)号：US20220005778A1

公开(公告)日：2022-01-06

申请号：US17361950

申请日：2021-06-29

Applicant: Infineon Technologies AG

Inventor： Swee Kah Lee ,  Sook Woon Chan ,  Fong Mei Lum ,  Joachim Mahler ,  Muhammad Muhammat Sanusi

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

公开(公告)号：US10461056B2

公开(公告)日：2019-10-29

申请号：US15600857

申请日：2017-05-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.