公开(公告)号：US20240063178A1

公开(公告)日：2024-02-22

申请号：US17821001

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Yi Shi ,  Tushar Talukdar ,  Feras Eid ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/08 ,  H01L2225/06548 ,  H01L2224/16227 ,  H01L2224/08145 ,  H01L2224/13116 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L24/13 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05613 ,  H01L2224/05609 ,  H01L2224/05605 ,  H01L24/05

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

公开(公告)号：US20240063143A1

公开(公告)日：2024-02-22

申请号：US17891690

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Lance C. Hibbeler ,  Omkar Karhade ,  Chytra Pawashe ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/3511

Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

公开(公告)号：US20240063142A1

公开(公告)日：2024-02-22

申请号：US17891666

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Botao Zhang ,  Yi Shi ,  Haris Khan Niazi ,  Feras Eid ,  Nagatoshi Tsunoda ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Omkar Karhade ,  Shawna Liff ,  Jiraporn Seangatith

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/367 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L25/0655 ,  H01L25/50

Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.

公开(公告)号：US20240063133A1

公开(公告)日：2024-02-22

申请号：US17891536

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Beomseok Choi ,  Feras Eid ,  Omkar Karhade ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/3128 ,  H01L21/56 ,  H01L21/4853 ,  H01L2924/1434 ,  H01L2924/1432 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08225 ,  H01L2224/08145

Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC: H01L23/46

CPC classification number: H01L23/46 ,  G02B6/4268

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.

公开(公告)号：US11895815B2

公开(公告)日：2024-02-06

申请号：US16909269

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel Elsherbini ,  Feras Eid

IPC: H01R12/53 ,  H05K9/00 ,  H01B7/18 ,  H01B7/00

CPC classification number: H05K9/0098 ,  H01B7/0018 ,  H01B7/1805 ,  H01R12/53

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.

公开(公告)号：US11791528B2

公开(公告)日：2023-10-17

申请号：US17714957

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

CPC classification number: H01P3/082 ,  H01P3/02 ,  H01P3/026 ,  H01P3/06 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088 ,  H05K1/0245

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20230317676A1

公开(公告)日：2023-10-05

申请号：US17711926

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Feras Eid ,  Wenhao Li ,  Zhaozhi Li ,  Pilin Liu

IPC: H01L23/00 ,  B23K20/02

CPC classification number: H01L24/75 ,  H01L24/81 ,  B23K20/023 ,  H01L2224/05647 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/75983 ,  H01L2224/75984 ,  H01L2224/75985 ,  H01L2224/75312 ,  H01L2224/75252 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/75253 ,  B23K2101/40

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) assembly including a bond head with a first thermal zone separated from a second thermal zone by a thermal separator, the thermal separator extending through a thickness of the bond head. A bond head nozzle is coupled to a first side of the bond head, where the bond head nozzle includes one or more nozzle channels extending through a thickness of the bond head nozzle.

公开(公告)号：US20230317675A1

公开(公告)日：2023-10-05

申请号：US17711925

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Zhaozhi Li ,  Feras Eid ,  Pilin Liu ,  Wenhao Li

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/81203 ,  H01L2224/75983 ,  H01L2224/75252

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) tool including a pedestal having a convex surface to receive a package substrate, a bond head to compress a die against the package substrate, and a heat source thermally coupled to at least one of the pedestal or the bond head.

公开(公告)号：US20230317630A1

公开(公告)日：2023-10-05

申请号：US17710502

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Michael Baker ,  Pilin Liu ,  Zhaozhi Li

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/81203

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.