公开(公告)号：US10199080B2

公开(公告)日：2019-02-05

申请号：US15485059

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/419

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

公开(公告)号：US09947388B2

公开(公告)日：2018-04-17

申请号：US15072278

申请日：2016-03-16

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Iqbal R. Rajwani ,  Eric K. Donkoh

IPC: G11C7/22 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.

公开(公告)号：US09755631B2

公开(公告)日：2017-09-05

申请号：US14951343

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Yong Shim ,  Jaydeep P. Kulkarni ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: G05F1/10 ,  H03K17/081 ,  H03K17/14 ,  H03K3/037

CPC classification number: H03K17/08104 ,  H03K3/0377 ,  H03K17/145 ,  H03K19/0016

Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

公开(公告)号：US20170243637A1

公开(公告)日：2017-08-24

申请号：US15495954

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US20170149427A1

公开(公告)日：2017-05-25

申请号：US14951343

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Yong Shim ,  Jaydeep P. Kulkarni ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03K17/081 ,  H03K3/037 ,  H03K17/14

CPC classification number: H03K17/08104 ,  H03K3/0377 ,  H03K17/145 ,  H03K19/0016

Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.

公开(公告)号：US10984855B2

公开(公告)日：2021-04-20

申请号：US16285057

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C8/10 ,  H01L27/11 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/00 ,  G11C29/02 ,  G11C8/08

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US20190206456A1

公开(公告)日：2019-07-04

申请号：US16234065

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

IPC: G11C7/12 ,  G11C15/04 ,  G11C11/412 ,  G11C8/16 ,  G11C7/18 ,  G11C11/419 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C15/04

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

公开(公告)号：US20180191347A1

公开(公告)日：2018-07-05

申请号：US15394296

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Andrea Bonetti ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Minki Cho ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03K19/0185 ,  H03K19/21

CPC classification number: H03K19/018521 ,  H03K19/21

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

公开(公告)号：US20170229161A1

公开(公告)日：2017-08-10

申请号：US15439800

申请日：2017-02-22

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Ashoke Ravi ,  Dinesh Somasekhar ,  Ganesh Balamurugan ,  Sudip Shekhar ,  Tawfiq Musah ,  Tzu-Chien Hsueh

IPC: G11C11/16 ,  H03K3/356 ,  H03M1/66 ,  H03H11/22 ,  G11C13/00 ,  H03M1/12

CPC classification number: G11C11/161 ,  G05F3/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H03H11/22 ,  H03K3/356104 ,  H03K19/018557 ,  H03K19/018585 ,  H03M1/12 ,  H03M1/362 ,  H03M1/66 ,  H03M1/765 ,  H04L25/00 ,  H04L25/03878

Abstract: Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

公开(公告)号：US09685208B2

公开(公告)日：2017-06-20

申请号：US15094755

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C17/16 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.