公开(公告)号：US09704839B2

公开(公告)日：2017-07-11

申请号：US14945170

申请日：2015-11-18

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans ,  Johann Gatterbauer ,  Thomas Gross ,  Martina Heigl

IPC: H01L33/00 ,  H01L25/16 ,  H01L33/62 ,  H01L33/60 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L31/055 ,  H01L33/40 ,  H01L33/46

CPC classification number: H01L25/167 ,  H01L21/76834 ,  H01L21/76877 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/552 ,  H01L24/03 ,  H01L24/06 ,  H01L27/14692 ,  H01L31/055 ,  H01L33/20 ,  H01L33/405 ,  H01L33/46 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/05144 ,  H01L2224/48227 ,  H01L2924/12041 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

公开(公告)号：US09209080B2

公开(公告)日：2015-12-08

申请号：US13715922

申请日：2012-12-14

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franco Mariani ,  Alexander Heinrich

IPC: H01L21/00 ,  H01L21/78 ,  H01L29/45 ,  H01L23/367

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/3677 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/45 ,  H01L2221/68327 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83191 ,  H01L2224/83365 ,  H01L2224/8382 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract translation: 半导体器件包括具有第一主面和第二主面的半导体芯片。 第二主面是半导体芯片的背面。 第二主面包括第一区域和第二区域。 第二区域是第二主面的周边区域，第一区域的高度和第二区域的高度不同。 第一区域可以用金属填充，并且可以被平坦化到与第二区域相同的水平。

公开(公告)号：US20240120298A1

公开(公告)日：2024-04-11

申请号：US17962131

申请日：2022-10-07

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L23/544

CPC classification number: H01L24/05 ,  H01L23/544 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/03001 ,  H01L2224/0346 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05566 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2924/01014 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/04941

Abstract: A semiconductor die includes: a semiconductor substrate; a first contact pad structure above the semiconductor substrate, the first contact pad structure including a metal contact pad configured for electrical contact and a metal layer adjoining an underside of the metal contact pad and jutting out beyond an edge of the metal contact pad; and a first optical detection marker in a periphery of the first contact pad structure and having a different contrast than the metal contact pad. The first optical detection marker includes a region of the metal layer that is adjacent to the edge of the metal contact pad and unobstructed by the metal contact pad so as to be optically visible in a plan view of the semiconductor die. A method of producing the semiconductor die is also described.

公开(公告)号：US10607972B2

公开(公告)日：2020-03-31

申请号：US15974299

申请日：2018-05-08

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans ,  Johann Gatterbauer ,  Thomas Gross ,  Martina Heigl

IPC: H01L25/16 ,  H01L27/146 ,  H01L33/20 ,  H01L23/552 ,  H01L33/44 ,  H01L33/38 ,  H01L51/52 ,  H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L31/055 ,  H01L33/40 ,  H01L33/46 ,  H01L33/60 ,  H01L33/62

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

公开(公告)号：US20190067209A1

公开(公告)日：2019-02-28

申请号：US15686576

申请日：2017-08-25

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.

公开(公告)号：US20170271313A1

公开(公告)日：2017-09-21

申请号：US15615031

申请日：2017-06-06

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Bernhard Weidgans ,  Johann Gatterbauer ,  Thomas Gross ,  Martina Heigl

IPC: H01L25/16 ,  H01L33/40 ,  H01L33/46 ,  H01L33/62 ,  H01L23/532 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L31/055 ,  H01L33/60

CPC classification number: H01L25/167 ,  H01L21/76834 ,  H01L21/76877 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/552 ,  H01L24/03 ,  H01L24/06 ,  H01L27/14692 ,  H01L31/055 ,  H01L33/20 ,  H01L33/405 ,  H01L33/46 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/05144 ,  H01L2224/48227 ,  H01L2924/12041 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

公开(公告)号：US09666546B1

公开(公告)日：2017-05-30

申请号：US15141571

申请日：2016-04-28

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/027 ,  H01L23/31 ,  H01L21/768

CPC classification number: H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US20170110423A1

公开(公告)日：2017-04-20

申请号：US15292219

申请日：2016-10-13

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans ,  Dietrich Bonart ,  Thomas Gross ,  Martina Debie

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/0272 ,  H01L21/0331 ,  H01L24/03 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171

Abstract: According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.

公开(公告)号：US09502248B1

公开(公告)日：2016-11-22

申请号：US14884869

申请日：2015-10-16

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans ,  Dietrich Bonart ,  Thomas Gross ,  Martina Debie

IPC: H01L21/44 ,  H01L21/033

CPC classification number: H01L24/05 ,  H01L21/0272 ,  H01L21/0331 ,  H01L24/03 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171

Abstract: According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.

Abstract translation: 根据各种实施例，一种方法可以包括：使用第一剥离过程在表面上形成第一层; 使用第二剥离工艺在所述第一层上形成第二层; 其中所述第二剥离过程被配置为使得所述第二层至少部分地覆盖所述第一层的至少一个侧壁。

公开(公告)号：US09293371B2

公开(公告)日：2016-03-22

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.