公开(公告)号：US10658566B2

公开(公告)日：2020-05-19

申请号：US16072166

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Feras Eid ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Baris Bicen ,  Thomas L. Sounart ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Valluri R. Rao

IPC: G02B26/00 ,  H01L41/09 ,  H01L27/32 ,  H05B45/00 ,  F21S10/02 ,  G02F1/01 ,  H01L41/22 ,  H01L51/00 ,  G06F3/041

Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.

公开(公告)号：US10453679B2

公开(公告)日：2019-10-22

申请号：US15748619

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L25/16 ,  H01L21/02 ,  H01L21/762 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L23/48 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/18

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

公开(公告)号：US09881990B2

公开(公告)日：2018-01-30

申请号：US15169665

申请日：2016-05-31

Applicant: INTEL CORPORATION

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01F5/00 ,  H01F27/06 ,  G09G5/00 ,  H01L49/02 ,  H01F7/08 ,  H01L23/48 ,  H01L23/522 ,  H01F17/00 ,  H01L21/768 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

公开(公告)号：US09419339B2

公开(公告)日：2016-08-16

申请号：US14918508

申请日：2015-10-20

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Valluri R. Rao ,  Ofir Degani

IPC: H04Q1/38 ,  H01Q9/04 ,  H01P11/00 ,  H01Q1/38 ,  H01Q1/22 ,  H01Q1/52 ,  H01Q21/00

CPC classification number: H01Q9/045 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01P11/00 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/526 ,  H01Q21/0006 ,  Y10T29/49018

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device.

公开(公告)号：US20190051562A1

公开(公告)日：2019-02-14

申请号：US16078663

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Valluri R. Rao ,  Han Wui Then

IPC: H01L21/8258 ,  H01L27/06 ,  H01L21/762

CPC classification number: H01L21/8258 ,  H01L21/76224 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/7851

Abstract: This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island.

公开(公告)号：US20190006171A1

公开(公告)日：2019-01-03

申请号：US15748619

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8258 ,  H01L27/085 ,  H01L23/48 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/187 ,  H01L21/76251 ,  H01L21/8258 ,  H01L23/481 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/7786

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

公开(公告)号：US09686861B2

公开(公告)日：2017-06-20

申请号：US15172029

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： Qing Ma ,  Quan A. Tran ,  Robert L. Sankman ,  Johanna M. Swan ,  Valluri R. Rao

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H05K3/46 ,  H01L23/15 ,  H05K3/00

CPC classification number: H05K1/112 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/15 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K3/0014 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10287 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0228 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

公开(公告)号：US09653805B2

公开(公告)日：2017-05-16

申请号：US14445662

申请日：2014-07-29

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Valluri R. Rao ,  Georgios Yorgos Palaskas

IPC: G01S19/53 ,  H01Q3/30 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q23/00 ,  H01L23/66 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01Q3/30 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15321 ,  H01Q1/2283 ,  H01Q9/0414 ,  H01Q21/065 ,  H01Q23/00 ,  Y10T29/49004 ,  Y10T29/49018

Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

公开(公告)号：US20170133364A9

公开(公告)日：2017-05-11

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L29/94 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/7787 ,  H01L29/94 ,  H01L29/945

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

公开(公告)号：US11421376B2

公开(公告)日：2022-08-23

申请号：US16072165

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Feras Eid ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Baris Bicen ,  Thomas L. Sounart ,  Valluri R. Rao ,  Johanna M. Swan

IPC: H01L41/047 ,  D06M10/06 ,  D06M11/46 ,  D06M11/47 ,  H01L41/316 ,  D06M17/00 ,  H01L41/087 ,  D06M11/83 ,  H01L41/187 ,  H01L41/29 ,  D01F11/00

Abstract: Embodiments of the invention include an active fiber with a piezoelectric layer that has a crystallization temperature that is greater than a melt or draw temperature of the fiber and methods of forming such active fibers. According to an embodiment, a first electrode is formed over an outer surface of a fiber. Embodiments may then include depositing a first amorphous piezoelectric layer over the first electrode. Thereafter, the first amorphous piezoelectric layer may be crystallized with a pulsed laser annealing process to form a first crystallized piezoelectric layer. In an embodiment, the pulsed laser annealing process may include exposing the first amorphous piezoelectric layer to radiation from an excimer laser with an energy density between approximately 10 and 100 mJ/cm2 and pulse width between approximately 10 and 50 nanoseconds. Embodiments may also include forming a second electrode over an outer surface of the crystallized piezoelectric layer.