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公开(公告)号：US09941175B2
公开(公告)日：2018-04-10
申请号：US15288017
申请日：2016-10-07
发明人： Huiming Bu , Shogo Mochizuki , Tenko Yamashita
IPC分类号： H01L29/78 , H01L21/84 , H01L29/66 , H01L29/06 , H01L21/02 , H01L21/762 , H01L27/12 , H01L21/311
CPC分类号： H01L29/1054 , H01L21/02107 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/31 , H01L21/31105 , H01L21/31116 , H01L21/76224 , H01L21/76248 , H01L21/845 , H01L27/1211 , H01L29/0653 , H01L29/0673 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.
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公开(公告)号：US09929057B2
公开(公告)日：2018-03-27
申请号：US15342801
申请日：2016-11-03
IPC分类号： H01L21/8234 , H01L21/768 , H01L27/088 , H01L29/66 , H01L21/02 , H01L21/311
CPC分类号： H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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公开(公告)号：US20170229558A1
公开(公告)日：2017-08-10
申请号：US15017868
申请日：2016-02-08
发明人： Brent A. Anderson , Huiming Bu , Fee Li Lie , Shogo Mochizuki , Junli Wang
IPC分类号： H01L29/66 , H01L29/78 , H01L21/308 , H01L29/417 , H01L21/306 , H01L21/324
CPC分类号： H01L29/66795 , H01L21/22 , H01L21/2254 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/3085 , H01L21/3086 , H01L21/324 , H01L21/84 , H01L27/1203 , H01L29/41791 , H01L29/42392 , H01L29/66553 , H01L29/66666 , H01L29/785 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.
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公开(公告)号：US20170148668A1
公开(公告)日：2017-05-25
申请号：US15426573
申请日：2017-02-07
IPC分类号： H01L21/768 , H01L29/66 , H01L21/8234 , H01L27/088 , H01L21/02 , H01L21/311
CPC分类号： H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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15.发明申请公开(公告)号：US20160336239A1
公开(公告)日：2016-11-17
申请号：US15060008
申请日：2016-03-03
IPC分类号： H01L21/84 , H01L21/02 , H01L21/265 , H01L21/308 , H01L29/66 , H01L49/02
CPC分类号： H01L21/845 , H01L21/26513 , H01L21/31053 , H01L21/32055 , H01L21/32139 , H01L27/0629 , H01L27/1211 , H01L28/20 , H01L29/66545 , H01L29/66795 , H01L29/7843
摘要： A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.
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16.发明申请SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE 审中-公开替代金属栅极晶体管器件中的源极 - 漏极扩展形成公开(公告)号：US20130161745A1
公开(公告)日：2013-06-27
申请号：US13628225
申请日：2012-09-27
发明人： Takashi Ando , Huiming Bu , Ramachandra Divakaruni , Bruce B. Doris , Chung-Hsun Lin , Huiling Shang , Tenko Yamashita
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L21/268 , H01L29/42384 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/78621
摘要： In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described.
摘要翻译： 在一个实施例中，晶体管结构包括设置在半导体本体的表面上的栅极堆叠。 栅极堆叠具有围绕栅极金属的栅极电介质层，并且覆盖半导体主体中的沟道区域。 晶体管结构还包括具有源极延伸区域和漏极的源极，该漏极延伸区域形成在半导体本体中，其中每个延伸区域具有与栅极叠层的边缘重叠的尖锐的突变结。 还包括在源极和漏极之间的半导体本体中的通道下方具有注入的掺杂物质的穿孔停止区域。 还存在具有位于穿通止动区域和通道之间的注入的掺杂剂物质的浅沟道区域。 描述了体半导体和绝缘体上硅晶体管实施例。
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公开(公告)号：US20130048988A1
公开(公告)日：2013-02-28
申请号：US13652804
申请日：2012-10-16
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.
摘要翻译： 提供了将纳米技术纳入电子保险丝（e-fuse）设计的技术。 一方面，提供了一种电熔丝结构。 电熔丝结构包括第一电极; 第一电极上的介电层，其中具有多个纳米通道; 金属硅化物纳米柱阵列，其填充介电层中的纳米通道，阵列中的每个纳米柱用作电熔丝元件; 以及与第一电极相对的金属硅化物纳米柱阵列接触的第二电极。 还提供了用于制造电熔丝结构的方法，其中还包括结合电熔丝结构的半导体器件。
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公开(公告)号：US20230411466A1
公开(公告)日：2023-12-21
申请号：US17664662
申请日：2022-05-24
发明人： Ruilong Xie , Kisik Choi , Junli Wang , SOMNATH GHOSH , Julien Frougier , Min Gyu Sung , Theodorus E. Standaert , Nicolas Jean Loubet , Huiming Bu
IPC分类号： H01L29/417 , H01L29/66 , H01L29/40
CPC分类号： H01L29/41733 , H01L29/78696 , H01L29/401 , H01L29/66742
摘要： A first source drain region adjacent to a first transistor, a second source drain region adjacent to a second transistor, an upper source drain contact above the first source drain region, a bottom source drain contact below the second source drain region, the bottom and the upper source drain contacts are on opposite sides, a horizontal surface of the bottom source drain contact is adjacent to a horizontal surface of dielectric side spacers surrounding the second source drain region. An embodiment where a bottom source drain contact surrounds vertical sides of a source drain region. A method including forming a forming a first and a second nanosheet stacks, forming a top source drain contact to a first source drain region adjacent to the first nanosheet stack, forming a bottom source drain contact to a lower horizontal surface of a second source drain region adjacent to the second nanosheet stack.
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公开(公告)号：US20230411289A1
公开(公告)日：2023-12-21
申请号：US17664663
申请日：2022-05-24
发明人： Ruilong Xie , Kisik Choi , Junli Wang , Somnath Ghosh , Julien Frougier , Min Gyu Sung , Theodorus E. Standaert , Nicolas Jean Loubet , Huiming Bu
IPC分类号： H01L23/528 , H01L23/48 , H01L23/535 , H01L29/06
CPC分类号： H01L23/5286 , H01L29/0665 , H01L23/535 , H01L23/481
摘要： A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.
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20.发明申请公开(公告)号：US20190355829A1
公开(公告)日：2019-11-21
申请号：US15982507
申请日：2018-05-17
发明人： Junli Wang , Veeraraghavan S. Basker , Huiming Bu
IPC分类号： H01L29/66 , H01L21/02 , H01L21/768 , H01L29/417 , H01L29/78
摘要： A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.
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