公开(公告)号：US20090115069A1

公开(公告)日：2009-05-07

申请号：US12172912

申请日：2008-07-14

Applicant: Young-Lyong KIM ,  Jong-Ho LEE ,  Min-Ho O

Inventor： Young-Lyong KIM ,  Jong-Ho LEE ,  Min-Ho O

IPC: H01L23/00 ,  H01L21/50 ,  H05K7/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2224/05599

Abstract: A semiconductor chip package having a molding layer is provided. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer. The semiconductor chip comprises a backside surface, side surfaces, and an active surface having a plurality of chip pads disposed thereon. The molding layer substantially covers the backside surface, the side surfaces, and the active surface of the semiconductor chip and defines at least one opening exposing a portion of the backside surface of the semiconductor chip. A multi-chip package including the semiconductor chip package and a method of manufacturing the semiconductor chip package are also provided.

Abstract translation: 提供具有成型层的半导体芯片封装。 半导体芯片封装包括半导体芯片，多个外部连接端子和成型层。 该半导体芯片包括背面，侧面以及其上设置有多个芯片焊盘的有源表面。 模制层基本上覆盖半导体芯片的背面，侧表面和有源表面，并且限定了暴露半导体芯片背面的一部分的至少一个开口。 还提供了包括半导体芯片封装的多芯片封装和制造半导体芯片封装的方法。

公开(公告)号：US20080308935A1

公开(公告)日：2008-12-18

申请号：US12141764

申请日：2008-06-18

Applicant: Young-Lyong KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Min-Ho O ,  Tae-Sung YOON ,  Cheol-Joon YOO

Inventor： Young-Lyong KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Min-Ho O ,  Tae-Sung YOON ,  Cheol-Joon YOO

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L21/566 ,  H01L23/3114 ,  H01L2224/16

Abstract: Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter.

Abstract translation: 提供半导体芯片封装，半导体封装及其制造方法。 在一些实施例中，半导体芯片封装包括包括有源表面，后表面和侧表面的半导体芯片，设置在形成在有源表面上的焊盘上的凸块焊球，以及设置成覆盖有源表面并暴露 凸块焊球的一部分。 相邻凸块焊球之间的成型层可以具有弯月面凹面，其中从活性表面到接触凸块焊球的弯液面凹面的边缘的高度约为相应凸块的最大直径的1/7长度 低于或高于具有最大直径的凸块焊球的部分的焊球。

公开(公告)号：US20080290513A1

公开(公告)日：2008-11-27

申请号：US12125391

申请日：2008-05-22

Applicant: Hyung-Jik BYUN ,  Jong-Gi LEE ,  Jong-Ho LEE ,  Se-Young YANG

Inventor： Hyung-Jik BYUN ,  Jong-Gi LEE ,  Jong-Ho LEE ,  Se-Young YANG

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided are a semiconductor package having molded balls on a bottom surface of a PCB and a method of manufacturing the semiconductor package. The semiconductor package includes: a semiconductor chip mounting member comprising circuit patterns on a first surface, an insulating layer defining openings exposing at least portions of the circuit patterns, and external contact terminals arranged on the portions of circuit patterns exposed by the openings; a semiconductor chip formed on a second surface of the semiconductor chip mounting member and electrically connected to the semiconductor chip mounting member; a first sealing portion coating the second surface of the semiconductor chip mounting member and the semiconductor chip; and a second sealing portion arranged on the insulating layer and the external contact terminals such that at least portions of the external contact terminals are exposed.

Abstract translation: 提供了一种在PCB的底表面上具有模制球的半导体封装以及半导体封装的制造方法。 所述半导体封装包括：半导体芯片安装构件，其包括在第一表面上的电路图案，绝缘层限定露出所述电路图案的至少一部分的开口以及布置在由所述开口暴露的所述电路图案部分上的外部接触端子; 半导体芯片，形成在所述半导体芯片安装构件的第二表面上并电连接到所述半导体芯片安装构件; 涂覆半导体芯片安装构件和半导体芯片的第二表面的第一密封部分; 以及布置在绝缘层和外部接触端子上的第二密封部分，使得外部接触端子的至少一部分露出。

公开(公告)号：US20070296067A1

公开(公告)日：2007-12-27

申请号：US11764072

申请日：2007-06-15

Applicant: Jong-Ho LEE ,  Young-Lyong KIM

Inventor： Jong-Ho LEE ,  Young-Lyong KIM

IPC: H01L23/495

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/06136 ,  H01L2224/11332 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/90 ,  H01L2224/9202 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2224/05552

Abstract: A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes a semiconductor chip and a circuit board. The semiconductor chip has a bond pad. The circuit board has a base substrate with a throughole, and a conductive film pattern placed on a sidewall of the throughole. The throughole is aligned with the bond pad to expose the bond pad. A connector located within the throughole electrically connects the conductive film pattern to the bond pad. A sealing layer covers the connector.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括半导体芯片和电路板。 半导体芯片具有接合焊盘。 电路板具有带有通孔的基底基板和位于通孔的侧壁上的导电膜图案。 通孔与接合焊盘对准以暴露接合焊盘。 位于通孔内的连接器将导电膜图案电连接到接合垫。 密封层覆盖连接器。

公开(公告)号：US20150243607A1

公开(公告)日：2015-08-27

申请号：US14490105

申请日：2014-09-18

Applicant: Jae-Gwon JANG ,  Jin-Woo PARK ,  Jong-Ho LEE

Inventor： Jae-Gwon JANG ,  Jin-Woo PARK ,  Jong-Ho LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/86 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48 ,  H01L2224/48228 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/48227

Abstract: A method of manufacturing a semiconductor package having a magnetic shield function is provided. The method includes forming cracks in a lattice structure on an active surface in which electrode terminals are formed; grinding a back surface of a wafer facing the active surface, bonding a tape on the active surface of the wafer, expanding the tape such that the wafer on the tape is divided as semiconductor chips, forming a shield layer on surfaces of the semiconductor chips and the tape, cutting the shield layer between the semiconductor chips and individualizing as each of the semiconductor chips which has a first shield pattern formed on back surface and sides, bonding the semiconductor chips on a substrate, and forming a second shield pattern on each of the active surfaces of the semiconductor chips, wherein the semiconductor chips and the substrate are physically and electrically connected by a bonding wire.

Abstract translation: 提供一种制造具有磁屏蔽功能的半导体封装的方法。 该方法包括在其中形成电极端子的有源表面上形成栅格结构中的裂纹; 研磨面向活性表面的晶片的背面，将胶带粘合在晶片的有效表面上，使胶带膨胀，使得胶带上的晶片被划分为半导体芯片，在半导体芯片的表面上形成屏蔽层， 在所述半导体芯片之间切割所述屏蔽层，并且将每个所述半导体芯片分别形成在所述半导体芯片的背面和侧面上形成第一屏蔽图案并且将所述半导体芯片接合在基板上，并在所述半导体芯片的每一个上形成第二屏蔽图案 半导体芯片的有源表面，其中半导体芯片和基板通过接合线物理和电连接。

公开(公告)号：US20150041913A1

公开(公告)日：2015-02-12

申请号：US14192074

申请日：2014-02-27

Applicant: Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

Inventor： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

IPC: H01L29/78 ,  H01L27/092

CPC classification number: H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

Abstract translation: 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20080096315A1

公开(公告)日：2008-04-24

申请号：US11623279

申请日：2007-01-15

Applicant: Se-Young JEONG ,  Nam-Seog KIM ,  Cha-Jea JO ,  Jong-Ho LEE ,  Myeong-Soon PARK

Inventor： Se-Young JEONG ,  Nam-Seog KIM ,  Cha-Jea JO ,  Jong-Ho LEE ,  Myeong-Soon PARK

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

Abstract translation: 提供一种堆叠式芯片封装及其形成方法。 间隔件形成在上芯片的一侧。 在间隔件上形成导线以电连接上芯片和下芯片。 堆叠式芯片封装的可靠性得到改善，因为引线接合不用于电连接上下芯片。 此外，堆叠的芯片封装的整体尺寸可以减小，因为接合线环的高度对整个堆叠的芯片封装高度没有贡献。

公开(公告)号：US20190251857A1

公开(公告)日：2019-08-15

申请号：US16342248

申请日：2017-10-13

Applicant: Jong-Ho LEE

Inventor： Jong-Ho LEE

IPC: G09B7/08 ,  G06F16/33 ,  G09B7/073

CPC classification number: G09B7/08 ,  G06F9/44 ,  G06F16/3341 ,  G06Q50/20 ,  G06Q50/2057 ,  G09B7/06 ,  G09B7/073

Abstract: Disclosed are a device and method for providing a checking question designed to allow a user to perform the checking study of correct answers or incorrect answers by using the choices of one or more incorrectly answered questions. The device includes: an incorrectly answered question selection unit which selects one or more questions incorrectly answered by a user from among questions provided to the user; a choice extraction unit which extracts correct answers as choices for the respective selected incorrectly answered questions; a checking question generation unit which generates one or more checking questions designed to allow the user to study the incorrectly answered questions by allocating the extracted choices so that the extracted choices become the choices of the checking questions; and a checking study provision unit which provides the study of the incorrectly answered questions by transmitting the generated checking questions to a user terminal.

公开(公告)号：US20150270177A1

公开(公告)日：2015-09-24

申请号：US14592842

申请日：2015-01-08

Applicant: Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

Inventor： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

IPC: H01L21/8238 ,  H01L29/40 ,  H01L21/324 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽; 在第一沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后进行退火; 退火后，依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数调整层和栅极导体; 并在栅极导体上形成覆盖层。

公开(公告)号：US20110121396A1

公开(公告)日：2011-05-26

申请号：US13010360

申请日：2011-01-20

Applicant: Jong-Ho LEE

Inventor： Jong-Ho LEE

IPC: H01L29/78

CPC classification number: G11C11/403 ,  H01L27/10876 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/78642 ,  H01L29/78648

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced.

Abstract translation: 提供了具有低泄漏电流的柱型场效应晶体管。 柱型场效应晶体管包括：半导体本体，形成在半导体柱中的源极和漏极; 形成在所述半导体主体的表面上的栅极绝缘层; 形成在栅极绝缘层的表面上的栅电极。 栅电极包括与第一栅电极电连接的第一栅电极和第二栅电极。 第一栅电极具有比第二栅电极高的功函数。 因此，可以减小栅极感应漏极泄漏（GIDL），从而可以大大降低截止状态的漏电流。