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11.
公开(公告)号:US11075127B2
公开(公告)日:2021-07-27
申请号:US16503270
申请日:2019-07-03
Applicant: Lam Research Corporation
Inventor: Seshasayee Varadarajan , Aaron R. Fellis , Andrew John McKerrow , James Samuel Sims , Ramesh Chandrasekharan , Jon Henri
IPC: H01L21/66 , H01L21/67 , H01L21/677 , H01L21/02 , C23C16/455 , C23C16/458 , C23C16/46 , C23C16/505 , C23C16/54 , C23C16/50 , C23C16/52
Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).
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12.
公开(公告)号:US20180047645A1
公开(公告)日:2018-02-15
申请号:US15232708
申请日:2016-08-09
Applicant: Lam Research Corporation
Inventor: Seshasayee Varadarajan , Aaron R. Fellis , Andrew John McKerrow , James Samuel Sims , Ramesh Chandrasekharan , Jon Henri
IPC: H01L21/66 , H01L21/02 , C23C16/52 , C23C16/50 , C23C16/455
CPC classification number: H01L22/20 , C23C16/45542 , C23C16/45544 , C23C16/4586 , C23C16/46 , C23C16/50 , C23C16/505 , C23C16/52 , C23C16/54 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/0228 , H01L21/67207 , H01L21/67248 , H01L21/67745
Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).
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公开(公告)号:US20170092856A1
公开(公告)日:2017-03-30
申请号:US14935317
申请日:2015-11-06
Applicant: LAM RESEARCH CORPORATION
Inventor: Jon Henri , Dennis M. Hausmann , Seshasayee Varadarajan , Bhadri N. Varadarajan
IPC: H01L45/00
CPC classification number: H01L45/16 , H01L45/06 , H01L45/065 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/142 , H01L45/143 , H01L45/144
Abstract: Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.
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公开(公告)号:US09353444B2
公开(公告)日:2016-05-31
申请号:US14225020
申请日:2014-03-25
Applicant: Lam Research Corporation
Inventor: Artur Kolics , Praveen Nalla , Seshasayee Varadarajan
IPC: C23C18/18 , H01L21/768 , C23C18/16 , C23C18/31 , C23C18/50
CPC classification number: C23C18/38 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1831 , C23C18/1872 , C23C18/31 , C23C18/32 , C23C18/36 , C23C18/42 , C23C18/44 , C23C18/50 , C23C18/54 , H01L21/288 , H01L21/76849 , H01L21/76871 , H01L21/76874 , H01L21/76879 , H01L21/76885
Abstract: A method for providing an electroless plating over at least one copper containing layer is provided. Surfaces of the at least one copper containing layer are sealed by selectively depositing a sealing layer of catalytically active metal on the at least one copper containing layer. The sealing layer is exposed to an electroless deposition bath that is more reactive to the catalytically active metal than to the at least one copper containing layer to provide an electroless deposition on the sealing layer.
Abstract translation: 提供了一种在至少一个含铜层上提供化学镀的方法。 通过在至少一个含铜层上选择性地沉积催化活性金属的密封层来密封至少一个含铜层的表面。 将密封层暴露于对催化活性金属反应性高于至少一个含铜层的无电沉积槽,以在密封层上提供无电沉积。
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公开(公告)号:US11970776B2
公开(公告)日:2024-04-30
申请号:US17310293
申请日:2020-01-27
Applicant: Lam Research Corporation
Inventor: Joshua Collins , Griffin John Kennedy , Hanna Bamnolker , Patrick A. van Cleemput , Seshasayee Varadarajan
IPC: C23C16/455 , C23C16/08 , C23C16/30 , C23C16/34 , C23C16/52 , H01L21/285 , H01L21/02
CPC classification number: C23C16/45553 , C23C16/08 , C23C16/308 , C23C16/34 , C23C16/45525 , C23C16/52 , H01L21/28568 , H01L21/02175 , H01L21/0228
Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.
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公开(公告)号:US11637037B2
公开(公告)日:2023-04-25
申请号:US16825473
申请日:2020-03-20
Applicant: Lam Research Corporation
IPC: H01L21/768 , H01L29/417 , H01L29/66 , H01L21/67 , H01L21/311 , H01L21/02 , H01L29/78
Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an Hz-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% Hz. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.
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公开(公告)号:US20220195598A1
公开(公告)日:2022-06-23
申请号:US17310293
申请日:2020-01-27
Applicant: Lam Research Corporation
Inventor: Joshua Collins , Griffin John Kennedy , Hanna Bamnolker , Patrick A. van Cleemput , Seshasayee Varadarajan
IPC: C23C16/455 , H01L21/285 , C23C16/30 , C23C16/34
Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.
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公开(公告)号:US10020188B2
公开(公告)日:2018-07-10
申请号:US15817579
申请日:2017-11-20
Applicant: LAM RESEARCH CORPORATION
Inventor: James S. Sims , Jon Henri , Ramesh Chandrasekharan , Andrew John McKerrow , Seshasayee Varadarajan , Kathryn Merced Kelchner
CPC classification number: H01L21/0228 , C23C16/0227 , C23C16/0272 , C23C16/345 , C23C16/402 , C23C16/4404 , C23C16/4405 , C23C16/45525 , C23C16/4554 , C23C16/50 , H01J37/32082 , H01J37/32467 , H01J37/32513 , H01J37/32532 , H01J37/3255 , H01J37/32715 , H01J37/32862 , H01J2237/3321 , H01J2237/335 , H01L21/0217 , H01L21/02211 , H01L21/02274
Abstract: A method of depositing ALD films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma such that aluminum-rich byproducts are formed on the ceramic surfaces, (b) depositing a conformal halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces so as to cover the aluminum-rich byproducts, (c) depositing a pre-coating on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film on the semiconductor substrate supported on the ceramic surface of the pedestal.
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公开(公告)号:US20230093011A1
公开(公告)日:2023-03-23
申请号:US17905104
申请日:2021-03-02
Applicant: Lam Research Corporation
Inventor: Andreas Fischer , Aaron Lynn Routzahn , Thorsten Bernd Lill , Seshasayee Varadarajan
IPC: H01L21/3213 , H01L21/67 , H01J37/32 , C23F1/02
Abstract: Molybdenum is etched in a highly controllable manner by performing one or more etch cycles, where each cycle involves exposing the substrate having a molybdenum layer to an oxygen-containing reactant to form molybdenum oxide followed by treatment with boron trichloride to convert molybdenum oxide to a volatile molybdenum oxychloride with subsequent treatment of the substrate with a fluorine-containing reactant to remove boron oxide that has formed in a previous reaction, from the surface of the substrate. In some embodiments the method is performed in an absence of plasma and results in a substantially isotropic etching. The method can be used in a variety of applications in semiconductor processing, such as in wordline isolation in 3D NAND fabrication.
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公开(公告)号:US10378107B2
公开(公告)日:2019-08-13
申请号:US14850816
申请日:2015-09-10
Applicant: Lam Research Corporation
Inventor: Ramesh Chandrasekharan , Saangrut Sangplung , Shankar Swaminathan , Frank Pasquale , Hu Kang , Adrien LaVoie , Edward Augustyniak , Yukinori Sakiyama , Chloe Baldasseroni , Seshasayee Varadarajan , Basha Sajjad , Jennifer L. Petraglia
IPC: C23C16/50 , C23C16/52 , H01J37/32 , C23C16/455
Abstract: A showerhead in a semiconductor processing apparatus can include faceplate through-holes configured to improve the flow uniformity during atomic layer deposition. The showerhead can include a faceplate having a plurality of through-holes for distributing gas onto a substrate, where the faceplate includes small diameter through-holes. For example, the diameter of each of the through-holes can be less than about 0.04 inches. In addition or in the alternative, the showerhead can include edge through-holes positioned circumferentially along a ring having a diameter greater than a diameter of the substrate being processed. The showerhead can be a low volume showerhead and can include a baffle proximate one or more gas inlets in communication with a plenum volume of the showerhead. The faceplate with small diameter through-holes and/or edge through-holes can improve overall film non-uniformity, improve azimuthal film non-uniformity at the edge of the substrate, and enable operation at higher RF powers.
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