公开(公告)号：US20210166996A1

公开(公告)日：2021-06-03

申请号：US17175006

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

公开(公告)号：US10777523B2

公开(公告)日：2020-09-15

申请号：US16387771

申请日：2019-04-18

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US10438928B2

公开(公告)日：2019-10-08

申请号：US14626575

申请日：2015-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

公开(公告)号：US20170358547A1

公开(公告)日：2017-12-14

申请号：US15687691

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/13 ,  H01L22/14 ,  H01L22/20 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02215 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03914 ,  H01L2224/03916 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05565 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/11632 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0474 ,  H01L2924/0503 ,  H01L2924/05994 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/05432

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US09780052B2

公开(公告)日：2017-10-03

申请号：US14853807

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/00 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02135 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/114 ,  H01L2224/11472 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053

Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

公开(公告)号：US20230403849A1

公开(公告)日：2023-12-14

申请号：US18366748

申请日：2023-08-08

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US11818888B2

公开(公告)日：2023-11-14

申请号：US17822036

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Anilkumar Chandolu

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11723196B2

公开(公告)日：2023-08-08

申请号：US17063101

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US11626388B2

公开(公告)日：2023-04-11

申请号：US17580521

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L21/76 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

公开(公告)号：US11482536B2

公开(公告)日：2022-10-25

申请号：US16937303

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.