Patent search ap:("Monolithic 3D Inc.") AND inv:"Zeev Wurman" Page 2

11.

发明申请
NOVEL SEMICONDUCTOR SYSTEM AND DEVICE 有权
Title translation: 新型半导体系统和器件

公开(公告)号：US20160111369A1

公开(公告)日：2016-04-21

申请号：US14975830

申请日：2015-12-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Zeev Wurman

IPC: H01L23/528 , H01L23/544 , H01L23/373 , H01L27/06

CPC classification number: H01L23/5286 , B82Y10/00 , G11C11/41 , G11C16/0408 , G11C16/0483 , G11C16/10 , G11C17/18 , G11C29/32 , G11C29/44 , H01L21/6835 , H01L21/76254 , H01L21/84 , H01L23/36 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L27/0207 , H01L27/0688 , H01L27/0694 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/10802 , H01L27/10894 , H01L27/10897 , H01L27/1104 , H01L27/1108 , H01L27/1116 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/1157 , H01L27/11573 , H01L27/11578 , H01L27/11807 , H01L27/1203 , H01L29/1033 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/785 , H01L29/78696 , H01L29/7881 , H01L29/792 , H01L2221/6835 , H01L2221/68381 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/81001 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00015 , H01L2924/014 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Abstract translation: 一种3D IC器件，包括：包括第一单结晶晶体管的第一半导体层，其中所述第一单结晶晶体管通过至少一个包括铝或铜的金属层互连; 第二层，包括第二单结晶晶体管并且覆盖所述至少一个金属层，其中所述至少一个金属层在所述第一半导体层和所述第二层之间; 全球电力网，用于向覆盖第二层的设备分配电力; 以及局部电网以将功率分配给第一单结晶晶体管，其中全局电网通过多个通过第二层通孔连接到本地电网，并且其中通孔具有小于150nm的半径。

12.

发明申请
SEMICONDUCTOR DEVICE AND STRUCTURE 有权
Title translation: 半导体器件和结构

公开(公告)号：US20150171079A1

公开(公告)日：2015-06-18

申请号：US14628231

申请日：2015-02-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Zeev Wurman

IPC: H01L27/06 , H01L23/50 , H01L23/34 , H01L23/48

CPC classification number: H01L27/0688 , H01L23/34 , H01L23/481 , H01L23/50 , H01L23/5252 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/0002 , H01L2924/15311 , H03K19/096 , H01L2924/00014 , H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure and a second clock origin, where the second clock origin is connected to the first clock distribution structure with a plurality of through layer vias, and where the second layer thickness is less than 1 micrometer.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分布结构，其中第二层包括第二时钟分布结构和第二时钟源，其中第二时钟源为连接到具有多个通过层通孔的第一时钟分配结构，并且其中第二层厚度小于1微米。

13.

发明授权
Automation for monolithic 3D devices 有权

公开(公告)号：US11514221B2

公开(公告)日：2022-11-29

申请号：US17712850

申请日：2022-04-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Zeev Wurman

IPC: G06F30/392 , G06F30/394 , G06F30/327

Abstract: A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least a first and a second level, where the first level includes logic and the second level includes memory; then performing a first placement of the second level using a placer executed by a computer, the placer is a part of a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the first level and the second level; and performing a second placement of the first level based on the first placement, where memory includes a first memory array, the logic includes a first logic circuit configured so as to write data to first memory array. Performing the first placement includes placing the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.

14.

发明授权
Automation for monolithic 3D devices 有权

公开(公告)号：US11341309B1

公开(公告)日：2022-05-24

申请号：US17581884

申请日：2022-01-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Zeev Wurman

IPC: G06F30/392 , G06F30/394 , G06F30/327

Abstract: A method of designing a 3D Integrated Circuit, including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer includes a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the logic and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit connected so to write data to the first memory array, where the first placement includes placement of the first memory array, and where the second placement includes placement of the first logic circuit based on the placement of the first memory array.

15.

发明授权
Automation for monolithic 3D devices 有权

公开(公告)号：US11030371B2

公开(公告)日：2021-06-08

申请号：US16149517

申请日：2018-10-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Zeev Wurman

IPC: G06F30/392 , G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata including logic and a memory strata including memory; then performing a first placement of the logic strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the memory strata based on the first placement, where the logic includes at least one decoder representation for the memory, where the at least one decoder representation has a virtual size with width of contacts for the through silicon vias, and where the performing a first placement includes using the decoder representation instead of an actual memory decoder.

16.

发明授权
3D semiconductor device 有权

公开(公告)号：US10910364B2

公开(公告)日：2021-02-02

申请号：US16242300

申请日：2019-01-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Zeev Wurman

IPC: H01L27/06 , H01L29/812 , H01L29/808 , H01L27/092 , H01L29/732 , H01L29/66 , H01L21/8238 , H01L21/768 , H01L29/786 , H01L29/45 , H01L29/423 , H01L23/367 , H01L27/12 , H01L27/118 , H01L27/11578 , H01L27/11551 , H01L27/112 , H01L27/11 , H01L27/108 , H01L27/105 , H01L27/02 , H01L23/544 , H01L23/48 , H01L21/84 , H01L21/822 , H01L21/762 , G03F9/00 , H01L23/532 , H01L23/528 , H01L23/522 , H01L27/11556 , H01L27/1157 , H01L45/00 , H01L27/24 , H01L27/11524 , H01L23/00 , H01L27/088 , H01L21/268 , H01L23/31

Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding, and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.

17.

发明授权
3D semiconductor device, fabrication method and system 有权

公开(公告)号：US10217667B2

公开(公告)日：2019-02-26

申请号：US15904347

申请日：2018-02-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Zeev Wurman

IPC: H01L21/822 , H01L25/065 , H01L21/683 , H01L29/786 , H01L29/78 , H01L21/84 , G11C29/00 , G11C17/06 , G11C16/04 , H03K19/177 , H03K19/0948 , H03K17/687 , H01L27/118 , H01L27/112 , H01L27/108 , H01L27/105 , H01L27/092 , H01L27/06 , H01L27/02 , H01L25/18 , H01L21/762 , H01L23/544 , H01L23/525 , H01L23/36 , G11C17/14 , H01L21/8238 , H01L27/11 , H01L23/00 , H01L23/48

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

18.

发明申请
3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

公开(公告)号：US20190006222A1

公开(公告)日：2019-01-03

申请号：US16101489

申请日：2018-08-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar , Zeev Wurman

IPC: H01L21/683 , H01L29/792 , G11C8/16 , H01L29/78 , H01L29/66 , H01L29/423 , H01L27/12 , H01L27/118 , H01L27/11578 , H01L27/11573 , H01L27/11551 , H01L27/11529 , H01L27/11526 , H01L27/112 , H01L27/11 , H01L27/108 , H01L27/105 , H01L27/10 , H01L27/092 , H01L27/06 , H01L27/02 , H01L23/525 , H01L23/48 , H01L21/84 , H01L21/8238 , H01L21/822 , H01L21/768 , H01L21/762 , H01L21/74 , H01L29/788 , H01L25/00 , H01L25/065 , H01L23/00 , H01L23/367

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.