公开(公告)号：US20180309417A1

公开(公告)日：2018-10-25

申请号：US15946552

申请日：2018-04-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/06 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H03F1/52 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/0274 ,  H01L21/2654 ,  H01L21/28575 ,  H01L21/30612 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/85 ,  H01L25/16 ,  H01L27/0248 ,  H01L27/0605 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/0664 ,  H01L29/045 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/207 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/66204 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371 ,  H01L29/861 ,  H01L29/8613 ,  H01L2224/0221 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05084 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0518 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/13051 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/19041 ,  H01L2924/19043 ,  H03F1/565 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/426 ,  H03F2200/444 ,  H03F2200/451 ,  H01L2924/00

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20180097092A1

公开(公告)日：2018-04-05

申请号：US15820897

申请日：2017-11-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Shigeru YOSHIDA ,  Masahiro SHIBATA

IPC: H01L29/737 ,  H01L29/12 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/737 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/12 ,  H01L29/20 ,  H01L29/401 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.

公开(公告)号：US20240347494A1

公开(公告)日：2024-10-17

申请号：US18756034

申请日：2024-06-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari SAJI ,  Atsushi KUROKAWA ,  Masahiro SHIBATA

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/07

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L25/072 ,  H01L24/13 ,  H01L2224/13014 ,  H01L2224/1601 ,  H01L2224/16137 ,  H01L2924/3512

Abstract: A semiconductor device includes a semiconductor substrate; at least one transistor located on the semiconductor substrate and including a plurality of semiconductor layers; an electrode provided for the transistor; an organic insulating film having an opening in a region overlapping the transistor and the electrode in plan view in a first direction perpendicular to the semiconductor substrate; and a bump located over the at least one transistor in plan view in the first direction and electrically connected to the electrode through the opening of the organic insulating film. The width of the bump in a second direction parallel to the semiconductor substrate is smaller than the width of the opening of the organic insulating film in the second direction.

公开(公告)号：US20240339425A1

公开(公告)日：2024-10-10

申请号：US18750258

申请日：2024-06-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari SAJI ,  Atsushi KUROKAWA ,  Masahiro SHIBATA

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L2224/13014 ,  H01L2224/13024 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/10329 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/3512

Abstract: A semiconductor device includes a semiconductor substrate, at least one transistor on the semiconductor substrate and including semiconductor layers, a wiring on the transistor, a first insulating film including a first opening in a region overlapping the transistor and the wiring in plan view in a first direction perpendicular to the semiconductor substrate, a first redistribution layer on the first insulating film, overlapping the at least one transistor in the first direction in plan view, and electrically connected to the wiring via the first opening, a second insulating film covering the first redistribution layer and the first insulating film and provided with a second opening in a region overlapping at least a part of the first redistribution layer in the first direction in plan view, and a bump electrically connected to the first redistribution layer via the second opening.

公开(公告)号：US20240153704A1

公开(公告)日：2024-05-09

申请号：US18503801

申请日：2023-11-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki TOKUYA ,  Masayuki AOIKE ,  Masahiro SHIBATA

IPC: H01G4/08 ,  H01G4/30 ,  H01G4/33

CPC classification number: H01G4/085 ,  H01G4/306 ,  H01G4/33

Abstract: A capacitor including a lower layer electrode, a dielectric film, and an upper layer electrode sequentially laminated on a partial area of an upper surface serving as one surface of a substrate formed from a compound semiconductor from a side closest to the substrate is disposed. A coating formed from an insulating metal oxide or a silicon oxide is disposed on or above the dielectric film. When the upper surface is viewed in a plan, the coating extends throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge.

公开(公告)号：US20210391233A1

公开(公告)日：2021-12-16

申请号：US17345581

申请日：2021-06-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari SAJI ,  Masahiro SHIBATA ,  Atsushi KUROKAWA

IPC: H01L23/36 ,  H01L29/737 ,  H01L23/48 ,  H01L23/00

Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.

公开(公告)号：US20200177140A1

公开(公告)日：2020-06-04

申请号：US16785482

申请日：2020-02-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20190296699A1

公开(公告)日：2019-09-26

申请号：US16435321

申请日：2019-06-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H03F3/195 ,  H01L29/417 ,  H01L27/06 ,  H01L29/737 ,  H03F3/213 ,  H01L29/04 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L29/861 ,  H01L21/265 ,  H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/027 ,  H01L21/3213 ,  H01L29/207 ,  H01L29/36 ,  H01L23/00 ,  H01L29/423 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H03F1/56

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20190172933A1

公开(公告)日：2019-06-06

申请号：US16207084

申请日：2018-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Shigeki KOYA ,  Masao KONDO ,  Takayuki TSUTSUI

IPC: H01L29/737 ,  H01L23/00 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66

Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

公开(公告)号：US20190006306A1

公开(公告)日：2019-01-03

申请号：US16006623

申请日：2018-06-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro SHIBATA ,  Daisuke TOKUDA ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Yasunari UMEMOTO

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05086 ,  H01L2224/05547 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082

Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.