公开(公告)号：US08093722B2

公开(公告)日：2012-01-10

申请号：US12905095

申请日：2010-10-15

申请人： Nan-Cheng Chen ,  Chih-Tai Hsu

发明人： Nan-Cheng Chen ,  Chih-Tai Hsu

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semiconductor die; a rewiring laminate structure comprising a re-routed metal layer between the first semiconductor die and the package carrier. At least a portion of the re-routed metal layer projects beyond the die edge. A plurality of bumps are arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

摘要翻译： 系统级封装包括封装载体; 具有裸片面和芯片边缘的第一半导体管芯，所述第一半导体管芯正面朝下装配到所述封装载体的芯片侧; 安装在第一半导体管芯旁边的第二半导体管芯; 重新布线层压结构，包括在第一半导体管芯和封装载体之间的重新布线的金属层。 重新布线的金属层的至少一部分突出超过模边。 在重新配线层叠结构上设置多个凸块，用于将第一半导体管芯与封装载体电连接。

公开(公告)号：US08039933B2

公开(公告)日：2011-10-18

申请号：US12840304

申请日：2010-07-21

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

摘要翻译： QFN半导体封装包括管芯附接垫; 安装在管芯附接垫上的半导体管芯; 设置在所述管芯附接垫附近的内部端子引线; 将内部端子引线接合到半导体管芯的第一引线; 延伸的外部端子引线，设置在所述QFN半导体封装的周围，其中所述延伸的外部端子引线设置在超过所述半导体管芯上的特定最小焊盘开口尺寸的最大焊丝长度之上; 设置在内端子引线和延伸外端子引线之间的中间端子; 将所述中间端子连接到所述半导体管芯的第二引线; 以及将中间终端连接到扩展的外部终端引线的第三引线。

公开(公告)号：US20100213588A1

公开(公告)日：2010-08-26

申请号：US12485923

申请日：2009-06-17

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495 ,  H01L23/498

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A wire bond chip package includes a chip carrier; a semiconductor die having a die face and a die edge, the semiconductor die being mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution bond pads; a plurality of bond wires interconnecting the redistribution bond pads with the chip carrier; and a mold cap encapsulating at least the semiconductor die and the bond wires.

摘要翻译： 引线键合芯片封装包括芯片载体; 具有裸片面和裸片边缘的半导体管芯，所述半导体管芯安装在所述芯片载体的管芯附着表面上，其中多个输入/输出（I / O）焊盘位于所述半导体管芯中或所述半导体管芯上; 在半导体管芯上的再布线层压结构，包括多个再分布接合焊盘的再布线层压结构; 将再分布接合焊盘与芯片载体互连的多个接合线; 以及至少封装半导体管芯和接合线的模具盖。

公开(公告)号：US20090190706A1

公开(公告)日：2009-07-30

申请号：US12010456

申请日：2008-01-25

申请人： Chung-Er Huang ,  Nan-Cheng Chen

发明人： Chung-Er Huang ,  Nan-Cheng Chen

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H01L25/16 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate module having an embedded phase-locked loop is cooperated with at least one function unit mounted thereon for forming an integrated system. The substrate module includes a base, a multi-layer structure, a built-in circuit unit, and an external circuit unit. The built-in circuit unit is integrated inside the multi-layer structure and the multi-layer structure is formed in the base. The external circuit unit is mounted on the upper surface of the base and is electrically coupled to the built-in circuit unit for jointly forming a phase-locked loop, so as to cooperate with the function unit.

摘要翻译： 具有嵌入式锁相环的衬底模块与安装在其上的至少一个功能单元配合以形成集成系统。 基板模块包括基座，多层结构，内置电路单元和外部电路单元。 内置电路单元集成在多层结构内，多层结构形成在底层。 外部电路单元安装在基座的上表面上，并且电耦合到内置电路单元，以共同形成锁相环，以便与功能单元配合。

公开(公告)号：US08749038B2

公开(公告)日：2014-06-10

申请号：US12010456

申请日：2008-01-25

申请人： Chung-Er Huang ,  Nan-Cheng Chen

发明人： Chung-Er Huang ,  Nan-Cheng Chen

IPC分类号： H01L23/02

CPC分类号： H03L7/06 ,  H01L25/16 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate module having an embedded phase-locked loop is cooperated with at least one function unit mounted thereon for forming an integrated system. The substrate module includes a base, a multi-layer structure, a built-in circuit unit, and an external circuit unit. The built-in circuit unit is integrated inside the multi-layer structure and the multi-layer structure is formed in the base. The external circuit unit is mounted on the upper surface of the base and is electrically coupled to the built-in circuit unit for jointly forming a phase-locked loop, so as to cooperate with the function unit.

摘要翻译： 具有嵌入式锁相环的衬底模块与安装在其上的至少一个功能单元配合以形成集成系统。 基板模块包括基座，多层结构，内置电路单元和外部电路单元。 内置电路单元集成在多层结构内，多层结构形成在底层。 外部电路单元安装在基座的上表面上，并且电耦合到内置电路单元，以共同形成锁相环，以便与功能单元配合。

公开(公告)号：US20110042794A1

公开(公告)日：2011-02-24

申请号：US12938390

申请日：2010-11-03

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/48

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19107 ,  H05K1/0206 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/611 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an outer terminal lead; an intermediary terminal disposed between the inner terminal lead and the outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the outer terminal lead. A circuit board includes a core layer; a first metal trace disposed over a first side of the core layer; and a first solder mask covering the first metal trace. The QFN package is mounted over the first solder mask. No metal pad of the first metal trace is formed within an area corresponding to the intermediary terminal.

摘要翻译： QFN封装包括具有凹陷区域的管芯附接垫; 安装在凹陷区域内的半导体管芯; 设置在所述管芯附接垫附近的内部端子引线; 将内部端子引线接合到半导体管芯的第一引线; 外部终端引线; 设置在内端子引线和外端子引线之间的中间端子; 将所述中间端子连接到所述半导体管芯的第二引线; 以及将中间端子连接到外部端子引线的第三线。 电路板包括芯层; 设置在所述芯层的第一侧上的第一金属迹线; 以及覆盖第一金属迹线的第一焊接掩模。 QFN封装安装在第一个焊接掩模上。 在对应于中间终端的区域内不形成第一金属迹线的金属焊盘。

公开(公告)号：US07838975B2

公开(公告)日：2010-11-23

申请号：US12370537

申请日：2009-02-12

申请人： Nan-Cheng Chen

发明人： Nan-Cheng Chen

IPC分类号： H01L23/52

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A flip-chip package includes a package carrier; a semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, and contact pads are situated on the die face; a rewiring laminate structure between the semiconductor die and the package carrier, the rewiring laminate structure including a re-routed metal layer, and at least a portion of the re-routed metal layer projects beyond the die edge; and bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier.

摘要翻译： 倒装芯片封装包括封装载体; 具有裸片面和芯片边缘的半导体管芯，半导体管芯正面朝下装配到封装载体的芯片侧，接触焊盘位于管芯面上; 在半导体管芯和封装载体之间的重新布线层叠结构，重新布线层压结构包括重新布线的金属层，并且至少一部分重新布线的金属层突出超过模具边缘; 以及布置在重新布线层压结构上的凸块，用于将半导体管芯与封装载体电连接。

公开(公告)号：US20100285638A1

公开(公告)日：2010-11-11

申请号：US12840308

申请日：2010-07-21

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L21/60 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead.

摘要翻译： 一种用于制造四边形扁平非引线（QFN）半导体封装的方法，包括半导体蚀刻载体的第一侧以形成引线阵列的顶部和管芯附接焊盘的管芯附着表面，其中引线阵列至少包括 一个内部端子引线设置成邻近管芯安装焊盘，沿着QFN半导体封装的周边设置的至少一个延伸的外部端子引线，以及设置在内部端子引线和延伸的外部端子引线之间的至少一个中间端子，其中 中间终端设置在内部端子引线和延伸的外部端子引线之间。

公开(公告)号：US20090283882A1

公开(公告)日：2009-11-19

申请号：US12390492

申请日：2009-02-22

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads.

摘要翻译： 四边形非引线（QFN）半导体封装包括具有凹陷区域的管芯附接焊盘; 安装在管芯附接垫的凹陷区域内的半导体管芯; 至少一列内部端子引线邻近管芯附接垫设置; 将所述内部端子引线分别连接到所述半导体管芯的第一引线; 至少一排沿QFN半导体封装的周边设置的延伸外端子引线; 设置在内部端子引线和延伸的外部端子引线之间的至少一排中间端子; 将所述中间端子分别连接到所述半导体管芯的第二配线; 以及将中间端子分别连接到扩展的外部端子引线的第三线。

公开(公告)号：US08310051B2

公开(公告)日：2012-11-13

申请号：US13280368

申请日：2011-10-25

申请人： Nan-Cheng Chen ,  Chih-Tai Hsu

发明人： Nan-Cheng Chen ,  Chih-Tai Hsu

IPC分类号： H01L23/52

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.

摘要翻译： 封装包装包括一个封装载体; 从封装载体的芯片侧面朝下组装的半导体芯片; 半导体管芯和封装载体之间的重新配线层叠结构; 布置在重新布线层压结构上的多个凸起，用于将半导体管芯与封装载体电连接; 以及安装在封装载体上的IC封装。 IC封装和半导体管芯至少部分重叠。