公开(公告)号：US20090190706A1

公开(公告)日：2009-07-30

申请号：US12010456

申请日：2008-01-25

申请人： Chung-Er Huang ,  Nan-Cheng Chen

发明人： Chung-Er Huang ,  Nan-Cheng Chen

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H01L25/16 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate module having an embedded phase-locked loop is cooperated with at least one function unit mounted thereon for forming an integrated system. The substrate module includes a base, a multi-layer structure, a built-in circuit unit, and an external circuit unit. The built-in circuit unit is integrated inside the multi-layer structure and the multi-layer structure is formed in the base. The external circuit unit is mounted on the upper surface of the base and is electrically coupled to the built-in circuit unit for jointly forming a phase-locked loop, so as to cooperate with the function unit.

摘要翻译： 具有嵌入式锁相环的衬底模块与安装在其上的至少一个功能单元配合以形成集成系统。 基板模块包括基座，多层结构，内置电路单元和外部电路单元。 内置电路单元集成在多层结构内，多层结构形成在底层。 外部电路单元安装在基座的上表面上，并且电耦合到内置电路单元，以共同形成锁相环，以便与功能单元配合。

公开(公告)号：US08749038B2

公开(公告)日：2014-06-10

申请号：US12010456

申请日：2008-01-25

申请人： Chung-Er Huang ,  Nan-Cheng Chen

发明人： Chung-Er Huang ,  Nan-Cheng Chen

IPC分类号： H01L23/02

CPC分类号： H03L7/06 ,  H01L25/16 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate module having an embedded phase-locked loop is cooperated with at least one function unit mounted thereon for forming an integrated system. The substrate module includes a base, a multi-layer structure, a built-in circuit unit, and an external circuit unit. The built-in circuit unit is integrated inside the multi-layer structure and the multi-layer structure is formed in the base. The external circuit unit is mounted on the upper surface of the base and is electrically coupled to the built-in circuit unit for jointly forming a phase-locked loop, so as to cooperate with the function unit.

摘要翻译： 具有嵌入式锁相环的衬底模块与安装在其上的至少一个功能单元配合以形成集成系统。 基板模块包括基座，多层结构，内置电路单元和外部电路单元。 内置电路单元集成在多层结构内，多层结构形成在底层。 外部电路单元安装在基座的上表面上，并且电耦合到内置电路单元，以共同形成锁相环，以便与功能单元配合。

公开(公告)号：US20130133193A1

公开(公告)日：2013-05-30

申请号：US13305502

申请日：2011-11-28

申请人： Chih-Tai Hsu ,  Nan-Cheng Chen ,  Chih-Ming Chiang ,  Hung-Chang Hung ,  Xin Zhong

发明人： Chih-Tai Hsu ,  Nan-Cheng Chen ,  Chih-Ming Chiang ,  Hung-Chang Hung ,  Xin Zhong

IPC分类号： H05K3/34 ,  H05K3/12

CPC分类号： H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/00015 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/1225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09427 ,  H05K2201/10803 ,  H05K2201/10969 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/53174 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.

摘要翻译： 本发明提供了一种用于高级四边形扁平无铅封装工艺的表面贴装技术工艺和与其一起使用的模板。 用于高级四边形扁平无铅封装的表面贴装技术工艺包括提供印刷电路板。 具有第一开口的模板安装在印刷电路板上。 印刷焊膏通过第一开口形成第一焊膏图案。 模具被取下。 执行部件放置处理以将包括管芯焊盘的高级四边形扁平无引线封装放置在印刷电路板上，其中第一焊膏图案接触管芯焊盘的下表面，并且将第一开口与 芯片焊盘的下表面在1:2与1:10之间。 进行回流处理以熔化第一焊膏图案以围绕管芯焊盘的侧壁。

公开(公告)号：US20120032314A1

公开(公告)日：2012-02-09

申请号：US13280368

申请日：2011-10-25

申请人： Nan-Cheng Chen ,  Chih-Tai Hsu

发明人： Nan-Cheng Chen ,  Chih-Tai Hsu

IPC分类号： H01L23/498 ,  H01L23/495

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.

摘要翻译： 封装包装包括一个封装载体; 从封装载体的芯片侧面朝下组装的半导体芯片; 半导体管芯和封装载体之间的重新配线层叠结构; 布置在重新布线层压结构上的多个凸起，用于将半导体管芯与封装载体电连接; 以及安装在封装载体上的IC封装。 IC封装和半导体管芯至少部分重叠。

公开(公告)号：US20110248394A1

公开(公告)日：2011-10-13

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US08093722B2

公开(公告)日：2012-01-10

申请号：US12905095

申请日：2010-10-15

申请人： Nan-Cheng Chen ,  Chih-Tai Hsu

发明人： Nan-Cheng Chen ,  Chih-Tai Hsu

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semiconductor die; a rewiring laminate structure comprising a re-routed metal layer between the first semiconductor die and the package carrier. At least a portion of the re-routed metal layer projects beyond the die edge. A plurality of bumps are arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

摘要翻译： 系统级封装包括封装载体; 具有裸片面和芯片边缘的第一半导体管芯，所述第一半导体管芯正面朝下装配到所述封装载体的芯片侧; 安装在第一半导体管芯旁边的第二半导体管芯; 重新布线层压结构，包括在第一半导体管芯和封装载体之间的重新布线的金属层。 重新布线的金属层的至少一部分突出超过模边。 在重新配线层叠结构上设置多个凸块，用于将第一半导体管芯与封装载体电连接。

公开(公告)号：US08039933B2

公开(公告)日：2011-10-18

申请号：US12840304

申请日：2010-07-21

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

摘要翻译： QFN半导体封装包括管芯附接垫; 安装在管芯附接垫上的半导体管芯; 设置在所述管芯附接垫附近的内部端子引线; 将内部端子引线接合到半导体管芯的第一引线; 延伸的外部端子引线，设置在所述QFN半导体封装的周围，其中所述延伸的外部端子引线设置在超过所述半导体管芯上的特定最小焊盘开口尺寸的最大焊丝长度之上; 设置在内端子引线和延伸外端子引线之间的中间端子; 将所述中间端子连接到所述半导体管芯的第二引线; 以及将中间终端连接到扩展的外部终端引线的第三引线。

公开(公告)号：US20100213588A1

公开(公告)日：2010-08-26

申请号：US12485923

申请日：2009-06-17

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495 ,  H01L23/498

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A wire bond chip package includes a chip carrier; a semiconductor die having a die face and a die edge, the semiconductor die being mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution bond pads; a plurality of bond wires interconnecting the redistribution bond pads with the chip carrier; and a mold cap encapsulating at least the semiconductor die and the bond wires.

摘要翻译： 引线键合芯片封装包括芯片载体; 具有裸片面和裸片边缘的半导体管芯，所述半导体管芯安装在所述芯片载体的管芯附着表面上，其中多个输入/输出（I / O）焊盘位于所述半导体管芯中或所述半导体管芯上; 在半导体管芯上的再布线层压结构，包括多个再分布接合焊盘的再布线层压结构; 将再分布接合焊盘与芯片载体互连的多个接合线; 以及至少封装半导体管芯和接合线的模具盖。

公开(公告)号：US20100207260A1

公开(公告)日：2010-08-19

申请号：US12766080

申请日：2010-04-23

申请人： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

发明人： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.

摘要翻译： 提供电子包装。 电子封装包括其上附着有管芯的管芯焊盘。 多个引线围绕芯片焊盘并与其间隔开以在其间限定环形间隙。 至少一个第一公共电极棒处于环形间隙中并且基本上与芯片焊盘共面，其中多个引线中的至少一个延伸到第一公共电极棒。 模塑料部分地封装芯片焊盘和第一公共电极棒，使得裸片焊盘和第一公共电极棒的底表面露出。 第一公共电极棒的长度基本上等于面对第一公共电极棒的模具一侧的多个电源或接地焊盘中的两个焊盘之间的预定距离。 还公开了一种具有电子封装的电子设备。

公开(公告)号：US08525310B2

公开(公告)日：2013-09-03

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。