公开(公告)号：US07332818B2

公开(公告)日：2008-02-19

申请号：US11127160

申请日：2005-05-12

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H01L23/538

CPC分类号： H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

摘要： An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.

摘要翻译： 一种电子封装，其包括具有定位在其上的至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 还提供了制造包装的方法，电路化基板和信息处理系统也是如此，后者适于将一个或多个电子包装作为其一部分。

公开(公告)号：US07145221B2

公开(公告)日：2006-12-05

申请号：US10920235

申请日：2004-08-18

申请人： Irving Memis ,  Kostas I. Papathomas

发明人： Irving Memis ,  Kostas I. Papathomas

IPC分类号： H01L23/58

CPC分类号： H01L23/145 ,  H01L21/48 ,  H01L21/50 ,  H01L23/4922 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0373 ,  H05K3/4602 ,  H05K2201/0209 ,  H01L2924/00

摘要： A circuitized substrate comprising a first layer comprised of a dielectric material including a low moisture absorptive polymer resin in combination with a nodular fluoropolymer web encased within the resin, the resulting dielectric layer formed from this combination not including continuous or semi-continuous fibers as part thereof. The substrate further includes at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

摘要翻译： 电路化基板，包括由介电材料构成的第一层，该电介质材料包括与包含在该树脂内的结节状氟聚合物纤维网结合的低吸水性聚合物树脂，由该组合形成的所得电介质层不包括连续或半连续纤维作为其一部分 。 衬底还包括位于电介质第一层上的至少一个电路化层。 还提供电气组件和制造基板的方法，如本发明的电路化基板作为其一部分的信息处理系统（例如，计算机）。

公开(公告)号：US06391210B2

公开(公告)日：2002-05-21

申请号：US09901848

申请日：2001-07-09

申请人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

发明人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

IPC分类号： H01B1300

CPC分类号： H05K3/4652 ,  H05K3/0023 ,  H05K3/0035 ,  H05K2203/0508 ,  H05K2203/0554

摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

摘要翻译： 一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。 还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。 该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。 要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有 基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

公开(公告)号：US5532024A

公开(公告)日：1996-07-02

申请号：US431545

申请日：1995-05-01

申请人： Steven F. Arndt ,  Luis J. Matienzo ,  Irving Memis ,  James Spalik ,  Tien Y. Wu

发明人： Steven F. Arndt ,  Luis J. Matienzo ,  Irving Memis ,  James Spalik ,  Tien Y. Wu

IPC分类号： C01G53/04 ,  B05D3/10 ,  C09J5/02 ,  C23C8/16 ,  C23C22/68 ,  B05D3/00 ,  B05D3/12

CPC分类号： B05D3/102 ,  C09J5/02 ,  C23C22/68 ,  B05D2202/40 ,  C09J2400/166

摘要： The present invention provides a novel method for improving the adhesion of polymers, particularly adhesives, to nickel surfaces. The method involves contacting the nickel surface with a hydrogen peroxide solution having a temperature of at least about 40.degree. C. for a time sufficient to form a wettable oxide surface having a water contact angle of less than about 10.degree..

摘要翻译： 本发明提供一种用于改善聚合物，特别是粘合剂对镍表面的粘合性的新方法。 该方法包括使镍表面与至少约40℃的温度的过氧化氢溶液接触一段足以形成具有小于约10°的水接触角的可湿性氧化物表面的时间。

公开(公告)号：US4233620A

公开(公告)日：1980-11-11

申请号：US16034

申请日：1979-02-27

申请人： Russell E. Darrow ,  Irving Memis ,  Richard M. Poliak

发明人： Russell E. Darrow ,  Irving Memis ,  Richard M. Poliak

IPC分类号： H01L23/055 ,  H01L23/10

CPC分类号： H01L23/055 ,  H01L23/10 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/10253

摘要： The hermetic seal of the backside of a substrate of an integrated circuit module is provided by a composition containing about 51.4 to about 60.6% by weight of an epoxy polymer; about 39 to about 48% by weight of a hardener and flexibilizing portion; and up to about 0.6% by weight of a coloring agent.

摘要翻译： 集成电路模块的基板的背面的气密密封由包含约51.4至约60.6重量％的环氧聚合物的组合物提供; 约39至约48重量％的硬化剂和增韧部分; 和至多约0.6重量％的着色剂。

公开(公告)号：US07470990B2

公开(公告)日：2008-12-30

申请号：US11086323

申请日：2005-03-23

申请人： Robert M. Japp ,  Irving Memis ,  Kostas I. Papathomas

发明人： Robert M. Japp ,  Irving Memis ,  Kostas I. Papathomas

IPC分类号： H01L23/52

CPC分类号： H01L23/3735 ,  H01L23/145 ,  H01L23/3733 ,  H01L23/4922 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/564 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/0278 ,  H05K2201/068

摘要： A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

摘要翻译： 一种电路化基板，包括复合层，所述复合层包括第一介电子层，所述第一介电子层包括具有低热膨胀系数的多个纤维和低吸湿性树脂的第二介电子层，所述第二介电子层不包括连续的或 半连续纤维等作为其一部分。 衬底还包括至少一个作为其一部分的导电层。 还提供电气组件和制造基板的方法，如本发明的电路化基板作为其一部分的信息处理系统（例如，计算机）。

公开(公告)号：US20080308923A1

公开(公告)日：2008-12-18

申请号：US12186767

申请日：2008-08-06

申请人： Jean Audet ,  Irving Memis

发明人： Jean Audet ,  Irving Memis

IPC分类号： H01L23/485

CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

摘要： A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

摘要翻译： 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出外，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。

公开(公告)号：US07294791B2

公开(公告)日：2007-11-13

申请号：US10953923

申请日：2004-09-29

申请人： Charles E. Danoski ,  Irving Memis ,  Steven G. Rosser

发明人： Charles E. Danoski ,  Irving Memis ,  Steven G. Rosser

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09663 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

摘要： A circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer. A method of making the substrate, and an electrical assembly and information handling system (e.g., computer) utilizing the substrate are also disclosed.

摘要翻译： 电路化基板被设计为基本上消除信号通过基板电路的信号线时的阻抗中断。 衬底包括具有多个导体的第一导电层，电组件可以在其上定位和电耦合。 这些焊盘在衬底内进一步耦合到信号线（例如，使用通孔），并且这些信号线还被进一步耦合到位于衬底内的另外多个导电衬垫。 信号线被定位成位于衬底的第一导电层和位于包括信号线的第二导电层下面的第三导电层内的电压平面之间。 可以在第三导电层的第一电压平面附近使用第二电压平面。 通孔也可用于将耦合到第一导体的信号线耦合到形成第三导电层的一部分的第二多个导体。 还公开了制造衬底的方法，以及利用衬底的电组件和信息处理系统（例如，计算机）。

公开(公告)号：US20060012054A1

公开(公告)日：2006-01-19

申请号：US11233572

申请日：2005-09-23

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H01L23/48

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

摘要翻译： 通过将来自芯片的信号重新定位到载体的上部信号层，可以改善信号从倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的逸出。 这涉及通过芯片载体将电路线从通过芯到芯片的芯片通过芯片的顶表面扇出，信号从载体离开印刷电路板，这是通过更好地利用表面积来实现的 核心和芯片之间的信号平面。 信号在每个顶部信号平面上被扇出，使得更多的信号通过芯中的通孔传输到底部信号平面，在那里它们可以逃逸到芯片的覆盖区域之外，从而增加了 电路逃离占地面积。

公开(公告)号：US06965170B2

公开(公告)日：2005-11-15

申请号：US10715690

申请日：2003-11-18

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.

摘要翻译： 通过将来自芯片的信号重新定位到载体的上部信号层，可以改善信号从倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的逸出。 这涉及从穿过芯片的顶表面通过芯片载体扇出电路线，通过芯到底表面，其中信号从载体离开印刷线路板。 通过更好地利用芯和芯片之间的信号平面的表面积来实现扇形化。 信号在每个顶部信号平面上扇出，使得更多的信号通过芯中的通孔传输到底部信号平面，在那里它们可以逃离到芯片的覆盖区域外部，从而增加电路的密度 逃离足迹区域。