公开(公告)号：US11854864B2

公开(公告)日：2023-12-26

申请号：US17530169

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyeon Kim ,  Hanmei Choi ,  Sukjin Chung ,  Bongjin Kuh ,  Changyong Kim ,  Hakyu Seong

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76229 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/76237

Abstract: A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto.

公开(公告)号：US11211284B2

公开(公告)日：2021-12-28

申请号：US16780810

申请日：2020-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyeon Kim ,  Hanmei Choi ,  Sukjin Chung ,  Bongjin Kuh ,  Changyong Kim ,  Hakyu Seong

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto.

公开(公告)号：US20210384217A1

公开(公告)日：2021-12-09

申请号：US17151383

申请日：2021-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US10903327B2

公开(公告)日：2021-01-26

申请号：US16859437

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L21/3213 ,  H01L29/423 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US09728666B2

公开(公告)日：2017-08-08

申请号：US14141547

申请日：2013-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongjin Kuh ,  Kichul Kim ,  JeongMeung Kim ,  Joonghan Shin ,  Jongsung Lim ,  Hanmei Choi

IPC: H01L31/0248 ,  H01L31/105 ,  H01L31/0224 ,  H01L31/0232 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/105 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03529 ,  H01L31/1808 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

Abstract: A semiconductor device includes a substrate, a first insulation layer formed on the substrate in a first region, a photon absorption seed layer formed on the first insulation layer in the first region and on the substrate in a second region separate from the first region, and a photon absorption layer formed on the photon absorption seed layer in the first region. The photon absorption seed layer has a particular structure that may assist in reducing dislocation density in a region that includes a photon absorption layer.

公开(公告)号：US20250081462A1

公开(公告)日：2025-03-06

申请号：US18952236

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US11888042B2

公开(公告)日：2024-01-30

申请号：US18094484

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L27/06 ,  H01L29/423 ,  H01L21/3213 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US09972636B2

公开(公告)日：2018-05-15

申请号：US15626395

申请日：2017-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC: H01L27/115 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/04

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US09564499B2

公开(公告)日：2017-02-07

申请号：US13972533

申请日：2013-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Soo Seol ,  Chanjin Park ,  Ki-Hyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Ju-Yul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/115 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Abstract translation: 三维半导体存储器件及其制造方法。 三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一 垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

公开(公告)号：US09443932B2

公开(公告)日：2016-09-13

申请号：US14330777

申请日：2014-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Chul Kim ,  Joonghan Shin ,  Bongjin Kuh ,  Taegon Kim ,  Hanmei Choi

IPC: H01L21/70 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0696 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a semiconductor substrate. Each of the unit cells may include a buried insulating pattern buried in the semiconductor substrate, a first active pattern provided on the buried insulating pattern, and a second active pattern provided on the buried insulating pattern and spaced apart from the first active pattern. The buried insulating pattern may define a unit cell region, in which each of the unit cells may be disposed.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括设置在半导体衬底上的多个单元电池。 每个单电池可以包括埋在半导体衬底中的掩埋绝缘图案，设置在掩埋绝缘图案上的第一有源图案和设置在掩埋绝缘图案上并与第一有源图案间隔开的第二有源图案。 埋置的绝缘图案可以限定单位单元区域，其中可以布置每个单位单元。