公开(公告)号：US09293218B2

公开(公告)日：2016-03-22

申请号：US14049399

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Yu ,  Sung-Min Seo ,  Ho-Young Song ,  Gil-Su Kim ,  Jong-Min Oh

IPC: G11C16/04 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C17/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。

公开(公告)号：US11169711B2

公开(公告)日：2021-11-09

申请号：US16524749

申请日：2019-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung Kim ,  Young-Hoon Son ,  Chan-Kyung Kim ,  Ho-Young Song ,  Jung Ho Ahn ,  Sang-Joon Hwang

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US10811077B2

公开(公告)日：2020-10-20

申请号：US16235638

申请日：2018-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon Shin ,  Do-Yeon Kim ,  Ho-Young Song ,  Dong-Su Lee

IPC: G11C11/406

Abstract: A memory device a plurality of memory banks, a hammer address manager, and a refresh controller. The hammer address manager manages access addresses with respect to the plurality of memory banks and provides a hammer address for a hammer refresh operation among the access addresses, the hammer address being the access address that is accessed more than other access addresses. The refresh controller generates a hammer refresh address signal based on the hammer address, the hammer refresh address signal corresponding to a row that is physically adjacent to a row corresponding to the hammer address such that the row physically adjacent to the row corresponding to the hammer address is refreshed by the hammer refresh operation.

公开(公告)号：US08897055B2

公开(公告)日：2014-11-25

申请号：US13771633

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

IPC: G11C17/16 ,  G11C29/00 ,  G11C7/10 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。

公开(公告)号：US11231996B2

公开(公告)日：2022-01-25

申请号：US17137535

申请日：2020-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US10860222B2

公开(公告)日：2020-12-08

申请号：US16354473

申请日：2019-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Shin ,  Do-Yeon Kim ,  Ho-Young Song

IPC: G06F3/06 ,  G11C11/406 ,  G06F12/02

Abstract: Provided are memory devices configured to perform row hammer handling operations, and memory systems including such memory devices. An example memory device may include a memory cell array including a plurality of memory cell rows; a row hammer handler that is configured to determine whether to perform a row hammer handling operation to refresh adjacent memory cell rows adjacent to a first row that is being intensively accessed from among the memory cell rows, resulting in a determination result; and a refresh manager configured to perform either a normal refresh operation for sequentially refreshing the memory cell rows or the row hammer handling operation, based on the determination result of the row hammer handler.

公开(公告)号：US09831003B2

公开(公告)日：2017-11-28

申请号：US15498855

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/36 ,  G11C29/42 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09792978B2

公开(公告)日：2017-10-17

申请号：US15341245

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Ho-Young Song

IPC: G11C16/06 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/408 ,  G06F3/06

CPC classification number: G11C11/4093 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40607 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.

公开(公告)号：US09659669B2

公开(公告)日：2017-05-23

申请号：US14698219

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09036441B2

公开(公告)日：2015-05-19

申请号：US13793457

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Oh ,  Ho-Young Song ,  Seong-Jin Jang

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C29/00

CPC classification number: G11C17/16 ,  G11C29/76

Abstract: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.

Abstract translation: 公开了一种其中可以在反熔丝电路外面监视反熔丝程序数据的反熔丝电路和包括反熔丝电路的半导体器件。 反熔丝电路包括反熔丝阵列，数据存储电路和第一选择电路。 反熔丝阵列包括一个或多个抗熔丝块，其包括具有多个反熔丝单元的第一反熔丝块，并且反熔丝阵列被配置为存储反熔丝程序数据。 数据存储电路被配置为通过一个或多个数据总线接收并存储来自反熔丝阵列的反熔丝程序数据。 第一选择电路被配置为响应于第一选择信号输出所述一个或多个反熔丝块的所选反熔丝块的反熔丝程序数据。