公开(公告)号：US20170125387A1

公开(公告)日：2017-05-04

申请号：US15402521

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： UN-BYOUNG KANG ,  Tae-Je Cho ,  Byung-Hyug Roh

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1413 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1713 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

公开(公告)号：US20240204026A1

公开(公告)日：2024-06-20

申请号：US18223307

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGHOON KANG ,  UN-BYOUNG KANG ,  SEUNGWAN SHIN ,  JUNG HYUN LEE

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14618 ,  H01L27/14623 ,  H01L27/14636

Abstract: An image sensor package according to an embodiment includes: a substrate including a metal portion; an image sensor chip on the substrate; and a transparent glass cover disposed on the substrate and including an upper plate and sidewalls, the upper plate and the sidewalls defined by a cavity at a lower portion and spaced from the image sensor chip, wherein the sidewalls are directly bonded to the metal portion of the substrate, and the image sensor chip is sealed by the transparent glass cover and the substrate.

公开(公告)号：US20230132272A1

公开(公告)日：2023-04-27

申请号：US17870898

申请日：2022-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN YOUNG OH ,  UN-BYOUNG KANG ,  BYEONGCHAN KIM ,  JUMYONG PARK ,  CHUNGSUN LEE

IPC: H01L23/00 ,  H01L25/065

Abstract: The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.

公开(公告)号：US20220208703A1

公开(公告)日：2022-06-30

申请号：US17697830

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  JIN HO AN ,  JONGHO LEE ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/00

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US20210005553A1

公开(公告)日：2021-01-07

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20200020641A1

公开(公告)日：2020-01-16

申请号：US16280186

申请日：2019-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONG-KWON KO ,  JUN-YEONG HEO ,  UN-BYOUNG KANG ,  JA-YEON LEE

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a first semiconductor device on an upper surface of the package substrate, a second semiconductor device on an upper surface of the first semiconductor device, a first connection bump attached to a lower surface of the package substrate, a second connection bump interposed between and electrically connected to the package substrate and the first semiconductor device, and a third connection bump interposed between and electrically connected to the first semiconductor device and the second semiconductor device. The first semiconductor device has an edge and a step at the edge.

公开(公告)号：US20240429205A1

公开(公告)日：2024-12-26

申请号：US18826592

申请日：2024-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-SICK PARK ,  UN-BYOUNG KANG ,  JONGHO LEE ,  TEAK HOON LEE

IPC: H01L25/065 ,  H01L23/00

Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

公开(公告)号：US20240222331A1

公开(公告)日：2024-07-04

申请号：US18473126

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-WOO PARK ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/0903 ,  H01L2224/09152 ,  H01L2224/16014 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/3511

Abstract: A semiconductor package includes a buffer chip configured to include a first dummy region and a second dummy region and to include first pads on rear surfaces of substrates of the first and second dummy regions; and a first core chip stacked at an upper portion of the buffer to include a bump 116 coupled to the first pad and positioned on an entire surface of the substrate, wherein the first pad is positioned in a line shape having a length including at least two bumps.

公开(公告)号：US20240105679A1

公开(公告)日：2024-03-28

申请号：US18135035

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  SANGHOON LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JUMYONG PARK ,  HYUNCHUL JUNG

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03 ,  H01L2224/08146 ,  H01L2225/06541

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.

公开(公告)号：US20230290718A1

公开(公告)日：2023-09-14

申请号：US18199824

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.