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11.发明授权Non-volatile memory array and method of using same for fractional word programming 有权非易失性存储器阵列及其分数字编程的使用方法公开(公告)号：US09123401B2
公开(公告)日：2015-09-01
申请号：US13652447
申请日：2012-10-15
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
CPC classification number: G11C5/145 , G11C8/08 , G11C11/5628 , G11C16/08 , G11C16/10
Abstract: A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.
Abstract translation: 包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。 非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。
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公开(公告)号：US20140269061A1
公开(公告)日：2014-09-18
申请号：US13958415
申请日：2013-08-02
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen , Vipin Tiwari
CPC classification number: G11C16/28 , G11C7/062 , G11C7/067 , G11C7/12 , G11C16/00 , G11C16/06 , G11C16/24 , G11C16/26 , G11C2207/063 , H01L27/11519
Abstract: Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed.
Abstract translation: 公开了用于高级纳米闪存器件的改进的感测电路和改进的位线布局。
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公开(公告)号：US11380698B2
公开(公告)日：2022-07-05
申请号：US17178520
申请日：2021-02-18
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC: G11C16/04 , H01L27/11526 , H01L27/11519 , H01L27/11521 , G11C16/14 , G11C16/26 , H01L29/423 , H01L29/788
Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
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公开(公告)号：US20210082516A1
公开(公告)日：2021-03-18
申请号：US16574059
申请日：2019-09-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
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公开(公告)号：US10325666B2
公开(公告)日：2019-06-18
申请号：US16218398
申请日：2018-12-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC: G11C7/00 , G11C16/30 , G11C16/08 , G11C16/04 , G11C16/14 , H01L27/11521 , G11C16/26 , G11C5/14 , G11C16/10 , G11C8/08 , G11C16/16
Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.
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Patent Agency Ranking
公开(公告)号：US10216242B2
公开(公告)日：2019-02-26
申请号：US15610612
申请日：2017-05-31
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
IPC: G11C5/14 , G06F1/26 , G06F1/28 , G11C7/20 , G11C16/30 , H03K19/0185 , G11C11/4074
Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.
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公开(公告)号：US09959927B2
公开(公告)日：2018-05-01
申请号：US15404087
申请日：2017-01-11
Inventor： Feng Zhou , Xian Liu , Nhan Do , Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten , Zhixian Chen , Wang Xinpeng , Guo-Qiang Lo
CPC classification number: G11C13/0007 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
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公开(公告)号：US09910473B2
公开(公告)日：2018-03-06
申请号：US13830246
申请日：2013-03-14
Applicant: Silicon Storage Technology, Inc.
Inventor： Hung Quoc Nguyen , Hieu Van Tran , Hung Thanh Nguyen
CPC classification number: G06F1/32 , G11C5/14 , G11C7/08 , G11C7/1072 , G11C7/20 , G11C7/222 , G11C2207/065 , G11C2207/2227
Abstract: An improved method and apparatus for performing power management in a memory device is disclosed.
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公开(公告)号：US09678553B2
公开(公告)日：2017-06-13
申请号：US15088038
申请日：2016-03-31
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
IPC: G11C5/14 , G06F1/26 , G06F1/28 , G11C7/20 , G11C16/30 , H03K19/0185 , G11C11/4074
CPC classification number: G06F1/266 , G06F1/28 , G11C5/14 , G11C5/143 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/4074 , G11C16/30 , H03K19/018521
Abstract: The invention relates to a system and method for improved power sequencing within an embedded flash memory device for a plurality of voltage sources. In one embodiment, a power sequence enabling circuit comprises a PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first voltage source. During a power up time period, a voltage output from the first voltage source ramps upward, toward a voltage output from a second voltage source through the PMOS transistor. During a power down period, a voltage from the second voltage source ramps downward toward an intermediate voltage greater than zero volts through the first NMOS transistor.
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公开(公告)号：US20170011810A1
公开(公告)日：2017-01-12
申请号：US15272417
申请日：2016-09-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
CPC classification number: G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
Abstract: A three-dimensional flash memory system is disclosed.
Abstract translation: 公开了三维闪存系统。
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