公开(公告)号：US20190115330A1

公开(公告)日：2019-04-18

申请号：US16211714

申请日：2018-12-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Liang Shih ,  Chun-Chong Chien ,  Hsin-Lung Chung ,  Te-Fang Chu

IPC: H01L25/16 ,  H01L23/552 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81

Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.

公开(公告)号：US20180247886A1

公开(公告)日：2018-08-30

申请号：US15590174

申请日：2017-05-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Hsien Chiu ,  Tsung-Hsien Tsai ,  Hsin-Lung Chung ,  Chen-Wen Huang ,  Fang-Hsien Shen

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: The disclosure provides a method for manufacturing an electronic package structure, including disposing on a carrier an electronic component and a conductive frame including a plurality of conductive pads and supporting parts; and covering the electronic component and the supporting parts of the conductive frame with an encapsulating layer while allowing the conductive pads to be exposed from the encapsulating layer, thereby increasing the efficiency and reducing the cost of manufacturing processes with the design of the conductive frame. The disclosure further provides the electronic package structure as described above.

公开(公告)号：US20170236787A1

公开(公告)日：2017-08-17

申请号：US15584281

申请日：2017-05-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Hsien Chiu ,  Hao-Ju Fang ,  Hsin-Lung Chung ,  Cho-Hsin Chang ,  Tsung-Hsien Tsai ,  Chia-Yang Chen ,  Chun-Chi Ke

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L21/78 ,  H01L23/16 ,  H01L23/31 ,  H01L21/56 ,  H01L21/54

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/54 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.

公开(公告)号：US09673151B2

公开(公告)日：2017-06-06

申请号：US14837604

申请日：2015-08-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Hsien Chiu ,  Hao-Ju Fang ,  Hsin-Lung Chung ,  Cho-Hsin Chang ,  Tsung-Hsien Tsai ,  Chia-Yang Chen ,  Chun-Chi Ke

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/54 ,  H01L21/56 ,  H01L21/78 ,  H01L23/16 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/54 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.

公开(公告)号：US09526171B2

公开(公告)日：2016-12-20

申请号：US14564180

申请日：2014-12-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Liang Shih ,  Hsin-Lung Chung ,  Te-Fang Chu ,  Hao-Ju Fang ,  Kuang-Neng Chung

IPC: H01L23/10 ,  H05K1/11 ,  H01L23/31 ,  H01L21/56

CPC classification number: H05K1/111 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/58 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.

Abstract translation: 提供了一种封装结构，其包括：具有相对的第一和第二表面的基板; 至少设置在所述基板的第一表面上的电子元件; 以及形成在所述基板的所述第一表面上以封装所述电子元件的密封剂。 密封剂具有非矩形形状，以减少密封剂中的无效空间。

公开(公告)号：US09257394B2

公开(公告)日：2016-02-09

申请号：US13919176

申请日：2013-06-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuang-Neng Chung ,  Hsin-Lung Chung ,  Tien-Chung Huang ,  Tsung-Hsien Hsu

IPC: H01L23/552 ,  H01L23/32 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2224/85

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供至少具有承载区域和限定在其表面上的切割区域的基板，其中所述切割区域围绕所述承载区域; 在所述基板的承载区域上设置至少一个电子元件; 在所述基板的承载区域设置具有凹部的至少一个定位构件的屏蔽件，并且所述电子元件容纳在所述凹部中，并且所述定位构件向外延伸到所述切割区域; 以及沿切割区域执行切割处理以去除定位构件和基底的部分。 因此，屏蔽件精确地定位在基板上。

公开(公告)号：US20140264958A1

公开(公告)日：2014-09-18

申请号：US13968834

申请日：2013-08-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tsung-Hsien Hsu ,  Hsin-Lung Chung ,  Te-Fang Chu ,  Kwok-Yan Lam ,  Shao-Meng Sim

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/295 ,  H01L23/291 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a substrate body; a semiconductor element disposed on the substrate body; and a molding compound forms on the substrate body for encapsulating the semiconductor element. The molding compound contains a metal oxide so as to have a high insulation impedance and a high heat dissipating rate and be capable of suppressing electromagnetic interference.

Abstract translation: 公开了一种半导体封装，其包括：基板主体; 设置在所述基板主体上的半导体元件; 并且在用于封装半导体元件的基板主体上形成模塑料。 模塑料含有金属氧化物以具有高绝缘阻抗和高散热率并且能够抑制电磁干扰。

公开(公告)号：US10062582B2

公开(公告)日：2018-08-28

申请号：US14817624

申请日：2015-08-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Chien-Cheng Lin

IPC: H01L21/60 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

公开(公告)号：US20170103953A1

公开(公告)日：2017-04-13

申请号：US15298480

申请日：2016-10-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Cho-Hsin Chang ,  Chia-Yang Chen ,  Chao-Ya Yang

IPC: H01L23/552 ,  H01L21/48 ,  H01L25/065 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic component, a first shielding layer formed on the encapsulant, and a second shielding layer formed on the first shielding layer. The first and second shielding layers are made of different materials. With the multiple shielding layers formed on the encapsulating layer, the electronic component is protected from electromagnetic interferences. The present invention also provides a method for fabricating the package structure.

公开(公告)号：US09343401B2

公开(公告)日：2016-05-17

申请号：US14256496

申请日：2014-04-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Liang Shih ,  Hsin-Lung Chung ,  Te-Fang Chu ,  Sheng-Ming Yang ,  Hung-Cheng Chen ,  Chia-Yang Chen

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32268 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring.

Abstract translation: 提供了一种制造半导体封装的方法，其包括以下步骤：提供具有多个焊盘和相对的第二表面的具有第一表面的封装基板; 在所述包装基板的第一表面上设置多个无源元件; 通过粘合膜将半导体芯片设置在无源元件上; 通过多个接合线电连接半导体芯片和接合焊盘; 以及在所述封装衬底的所述第一表面上形成密封剂以封装所述半导体芯片，所述无源元件和所述接合线。 通过在封装基板和半导体芯片之间配置无源元件，本发明节约了封装基板上的空间，增加了布线灵活性。 此外，由于接合线不容易与无源元件接触，所以本发明防止发生短路。