公开(公告)号：US20190244653A1

公开(公告)日：2019-08-08

申请号：US16336175

申请日：2017-09-07

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： MASANORI TSUKAMOTO

IPC分类号： G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11502

CPC分类号： G11C11/221 ,  G11C11/22 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11587 ,  H01L27/1159

摘要： [Object] To provide a semiconductor storage element that has a more reduced planar area.[Solution] A semiconductor storage element including: a memory cell transistor including a gate insulator film at least partially including ferroelectric material; and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.

公开(公告)号：US20190115354A1

公开(公告)日：2019-04-18

申请号：US15730742

申请日：2017-10-12

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Shyue Seng TAN ,  Kiok Boone Elgin QUEK ,  Eng Huat TOH

IPC分类号： H01L27/11521 ,  H01L29/08 ,  H01L29/788 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/10 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1159 ,  H01L28/55 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/788 ,  H01L29/7881

摘要： Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.

公开(公告)号：US20190019683A1

公开(公告)日：2019-01-17

申请号：US16016602

申请日：2018-06-24

申请人： SK hynix Inc.

发明人： Hyangkeun YOO

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L27/1159 ,  G11C11/22 ,  H01L29/78

CPC分类号： H01L29/40111 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/31155 ,  H01L27/1159 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory device is provided. The method includes preparing a substrate, forming an interfacial insulation layer on the substrate, forming a ferroelectric layer on the interfacial insulation layer, applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer, forming a gate electrode layer on the ferroelectric layer, and annealing the ferroelectric layer to crystallize the ferroelectric layer.

公开(公告)号：US20180323188A1

公开(公告)日：2018-11-08

申请号：US15585876

申请日：2017-05-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jin-Ping Han ,  Yulong Li ,  Dennis M. Newns ,  Paul M. Solomon ,  Xiao Sun

IPC分类号： H01L27/06 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC分类号： H01L27/0629 ,  H01L21/28291 ,  H01L27/11507 ,  H01L27/1159

摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

公开(公告)号：US20180277550A1

公开(公告)日：2018-09-27

申请号：US15839849

申请日：2017-12-13

申请人： SK hynix Inc.

发明人： Hyangkeun YOO

IPC分类号： H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22 ,  H01L29/49

CPC分类号： H01L27/1159 ,  G11C11/223 ,  G11C11/2275 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

摘要： A ferroelectric memory device includes a substrate, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer.

公开(公告)号：US20180265967A1

公开(公告)日：2018-09-20

申请号：US15914962

申请日：2018-03-07

申请人： Versum Materials US, LLC

发明人： Xinjian Lei ,  Matthew R. MacDonald ,  Moo-Sung Kim ,  Se-Won Lee

IPC分类号： C23C16/40 ,  H01L21/02 ,  C23C16/455

CPC分类号： C23C16/405 ,  C23C16/401 ,  C23C16/45527 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45542 ,  C23C16/45553 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02345 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159

摘要： In one aspect, the invention is formulations comprising both organoaminohafnium and organoaminosilane precursor compounds that allows anchoring both silicon-containing fragments and hafnium-containing fragments onto a given surface having hydroxyl groups to deposit silicon doped hafnium oxide having a silicon doping level ranging from 0.5 to 8 mol %, suitable as ferroelectric material. In another aspect, the invention is methods and systems for depositing the silicon doped hafnium oxide films as ferroelectric materials using the formulations.

公开(公告)号：US20180226428A1

公开(公告)日：2018-08-09

申请号：US15944270

申请日：2018-04-03

申请人： Micron Technology, Inc.

发明人： Ferdinando Bedeschi

IPC分类号： H01L27/11597 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11587 ,  H01L27/1159

CPC分类号： H01L27/11597 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78391

摘要： A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

公开(公告)号：US20180226417A1

公开(公告)日：2018-08-09

申请号：US15815326

申请日：2017-11-16

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L27/11507 ,  H01L21/8238 ,  H01L29/08 ,  H01L49/02 ,  H01L27/092 ,  H01L27/06 ,  H01L29/06

CPC分类号： H01L27/11507 ,  H01L21/28291 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/11587 ,  H01L27/1159 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/0847

摘要： After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

公开(公告)号：US20180226416A1

公开(公告)日：2018-08-09

申请号：US15815312

申请日：2017-11-16

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L27/11507 ,  H01L21/8238 ,  H01L29/08 ,  H01L49/02 ,  H01L27/092 ,  H01L27/06 ,  H01L29/06

CPC分类号： H01L27/11507 ,  H01L21/28291 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/11587 ,  H01L27/1159 ,  H01L28/55 ,  H01L28/82 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/0847

摘要： After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

公开(公告)号：US20180151746A1

公开(公告)日：2018-05-31

申请号：US15640127

申请日：2017-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Chi Tu ,  Jen-Sheng YANG ,  Sheng-Hung SHIH ,  Tong-Chern ONG ,  Wen-Ting CHU

IPC分类号： H01L29/78 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22

CPC分类号： H01L29/78391 ,  G11C11/223 ,  G11C11/2257 ,  G11C11/2273 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/6684

摘要： A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.