公开(公告)号：US5731603A

公开(公告)日：1998-03-24

申请号：US701500

申请日：1996-08-22

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

公开(公告)号：US5661314A

公开(公告)日：1997-08-26

申请号：US316112

申请日：1994-09-30

申请人： Perry Merrill ,  Herbert J. Gould

发明人： Perry Merrill ,  Herbert J. Gould

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66333 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/7802 ,  H01L29/0847

摘要： A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5.times.10.sup.12 atoms per centimeter squared and is driven for about 10 hours at 1175.degree. C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.

摘要翻译： 蜂窝绝缘栅双极晶体管（“IGBT”）器件在间隔开的基极之间的有源区域中增加浓度，使得其深度大于基极区域的深度。 作为增加浓度的来源的植入剂量为每平方厘米约3.5x1012原子，并在1175℃下驱动约10小时。通过增加辐射剂量来降低寿命以减少开关损耗而不降低击穿电压或向前增加 电压降高于以前的水平。 增加的浓度区域允许减小基极之间的间隔并且提供低局部双极增益的区域，增加器件锁存电流。 在关闭感性负载时，器件可以成功吸收的雪崩能量显着增加。 在新的结合图案的新工艺中，在体和源区之前形成非常深的增加的导电区。

公开(公告)号：US5198688A

公开(公告)日：1993-03-30

申请号：US921393

申请日：1992-07-30

申请人： Kazuhiro Tsuchiya ,  Yutaka Yoshida

发明人： Kazuhiro Tsuchiya ,  Yutaka Yoshida

IPC分类号： H01L29/739

CPC分类号： H01L29/7398 ,  H01L29/7393

摘要： A semiconductive device of the type including a conductivity-modulated field-effect transistor provides all of the three electrodes on the principal surface by use of a buried layer and a variety of means for restricting device current to flow through the buried layer. Some of the arrangements not only overcome some effects of parasitic transistors that are formed, but obtain faster turn-on and turn-off while retaining the desired current capacity of the device. The arrangements include means for stopping the lateral spread of a depletion region, a minority carrier suppression region, and drain wall arrangements, among others.

摘要翻译： 包括导电调制场效应晶体管的类型的半导体器件通过使用掩埋层和用于限制器件电流流过掩埋层的各种装置在主表面上提供所有三个电极。 一些布置不仅克服形成的寄生晶体管的一些影响，而且在保持器件的期望电流容量的同时获得更快的导通和关断。 这些布置包括用于停止耗尽区域，少数载体抑制区域和排水壁布置等的横向扩展的装置。

公开(公告)号：US5060032A

公开(公告)日：1991-10-22

申请号：US611453

申请日：1990-11-13

申请人： Kenji Ogawa

发明人： Kenji Ogawa

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/68 ,  H01L29/739 ,  H01L29/8605

CPC分类号： H01L29/0834 ,  H01L29/41716 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/8605

摘要： A transistor having a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed in the semiconductor substrate, a source region of the first conductivity type, a gate electrode formed on the base region between the source region and the semiconductor substrate via a gate insulator film, an additional region of the second conductivity type formed in the semiconductor substrate but separated from the base region, a resistive layer formed in electrical contact with an area of the semiconductor substrate which is separated from the base region and the additional region, a source electrode connected with the source region and a drain electrode connected with the additional region and the resistive layer.

公开(公告)号：US10079278B2

公开(公告)日：2018-09-18

申请号：US15278816

申请日：2016-09-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC分类号： H01L29/06 ,  H01L29/735 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L29/167 ,  H01L29/739 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

摘要： A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

公开(公告)号：US20180102424A1

公开(公告)日：2018-04-12

申请号：US15831112

申请日：2017-12-04

申请人： Texas Instruments Incorporated

发明人： Yufei XIONG ,  Yunlong LIU ,  Hong YANG ,  Ho LIN ,  Tian Ping LV ,  Sheng ZOU ,  Qiu Ling JIA

IPC分类号： H01L29/739 ,  H01L21/3213 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7397 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/743 ,  H01L23/485 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7827

摘要： A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US20160268421A1

公开(公告)日：2016-09-15

申请号：US14836721

申请日：2015-08-26

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hitoshi SHINOHARA

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L23/48 ,  H01L29/739 ,  H01L23/00

CPC分类号： H01L29/7813 ,  H01L23/481 ,  H01L24/13 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7398 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first region of a first conductivity type provided along the first surface selectively on a second region of a second conductivity type formed along the first surface, and a third region of a first conductivity type between the second region and the second surface. The semiconductor device also includes a gate electrode adjacent to the second region. First, second, and third electrode pads are formed along the second surface. The first pad is electrically connected by a first via through the substrate to first region. The third electrode pad is electrically connected by a second via through the substrate to the gate electrode.

摘要翻译： 半导体器件包括具有第一表面和与第一表面相对的第二表面的半导体衬底，沿第一表面形成的第二导电类型的第二区域沿着第一表面设置的第一导电类型的第一区域， 以及在所述第二区域和所述第二表面之间的第一导电类型的第三区域。 半导体器件还包括与第二区域相邻的栅电极。 沿着第二表面形成第一，第二和第三电极焊盘。 第一焊盘通过第一通孔通过衬底电连接到第一区域。 第三电极焊盘通过基板的第二通孔电连接到栅电极。

公开(公告)号：US09306042B2

公开(公告)日：2016-04-05

申请号：US14182930

申请日：2014-02-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC分类号： H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L29/167 ,  H01L29/10

CPC分类号： H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

摘要： A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

公开(公告)号：US09263369B2

公开(公告)日：2016-02-16

申请号：US13835227

申请日：2013-03-15

申请人： Infineon Technologies Austria AG

发明人： Khalil Hosseini ,  Anton Mauder ,  Joachim Mahler

IPC分类号： H01L21/56 ,  H01L23/48 ,  H01L21/768 ,  H01L25/07 ,  H01L25/18 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/074 ,  H01L25/18 ,  H01L29/66333 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/861 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure.

摘要翻译： 各种实施例提供了芯片布置。 芯片布置可以包括具有第一芯片侧和与第一芯片侧相对的第二芯片侧的第一芯片和在其第二芯片侧的至少一个触点; 第二芯片，具有与第一芯片侧相对的第一芯片侧和第二芯片侧以及在其第一芯片侧的至少一个触点; 其中，所述第一芯片的所述第二芯片侧和所述第二芯片的所述第二芯片侧面对; 第一导电结构，其从第一芯片的至少一个触点从第一芯片的第二芯片侧延伸穿过第一芯片到第一芯片的第一芯片侧; 和第二导电结构。

公开(公告)号：US20150179631A1

公开(公告)日：2015-06-25

申请号：US14140291

申请日：2013-12-24

申请人： MACRONIX International Co., Ltd.

发明人： Ying-Chieh Tsai ,  Wing-Chor Chan ,  Jeng Gong

IPC分类号： H01L27/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/0623 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L29/0642 ,  H01L29/1004 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7398 ,  H01L29/7816

摘要： Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region.

摘要翻译： 提供了一种半导体器件，包括第一导电类型的深掺杂区域，第二导电类型的阱区域，第一导电类型的基极区域，绝缘栅双极晶体管（IGBT）和金属氧化物半导体（MOS） 。 阱区设置在深掺杂区域中。 基极区域设置在阱区中并且不连接到深掺杂区域。 IGBT设置在基极区域的第一侧的阱区上，并且包括设置在基极区域中的第二导电类型的第一掺杂区域。 MOS设置在基极区域的第二侧的阱区域和深阱区域，并且包括设置在基极区域中的第二导电类型的第二掺杂区域。