公开(公告)号：US09905651B2

公开(公告)日：2018-02-27

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niti Goel ,  Van H. Le ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Stephen M. Cea ,  Robert S. Chau

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US09818884B2

公开(公告)日：2017-11-14

申请号：US15120818

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Willy Rachmady ,  Harold W. Kennel

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/786 ,  H01L21/02 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/15

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/155 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

Abstract: An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.

公开(公告)号：US20170221999A1

公开(公告)日：2017-08-03

申请号：US15492785

申请日：2017-04-20

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L29/04 ,  H01L29/06

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

公开(公告)号：US20170179228A1

公开(公告)日：2017-06-22

申请号：US15447044

申请日：2017-03-01

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/15 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US09685381B2

公开(公告)日：2017-06-20

申请号：US14777736

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L21/8238 ,  H01L29/267 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795

Abstract: Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

公开(公告)号：US09673045B2

公开(公告)日：2017-06-06

申请号：US14908112

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8258 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

公开(公告)号：US09666708B2

公开(公告)日：2017-05-30

申请号：US15120705

申请日：2014-03-26

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Robert S. Chau ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/02 ,  H01L21/033 ,  H01L29/08 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0332 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

公开(公告)号：US20170133493A1

公开(公告)日：2017-05-11

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US09640622B2

公开(公告)日：2017-05-02

申请号：US14778574

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L31/102 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US20170104094A1

公开(公告)日：2017-04-13

申请号：US15389255

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/40 ,  H01L21/02 ,  H01L29/36 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/268 ,  H01L29/20 ,  H01L21/306

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.