公开(公告)号：US09027400B2

公开(公告)日：2015-05-12

申请号：US13310477

申请日：2011-12-02

Applicant: Olivier Le Neel ,  Suman Cherian ,  Ravi Shankar ,  Boon Nam Poh ,  Sebastien Marsanne ,  Michele Vaiana

Inventor： Olivier Le Neel ,  Suman Cherian ,  Ravi Shankar ,  Boon Nam Poh ,  Sebastien Marsanne ,  Michele Vaiana

IPC: G01N27/22

CPC classification number: G01N27/223

Abstract: A capacitive humidity sensor includes a first electrode, a humidity sensitive dielectric layer, and a second electrode. The humidity sensitive dielectric layer is between the first and the second electrodes. The humidity sensitive dielectric layer is etched at selected regions to form hollow regions between the first and second electrodes.

Abstract translation: 电容式湿度传感器包括第一电极，湿度敏感介电层和第二电极。 湿敏电介质层位于第一和第二电极之间。 在选定的区域蚀刻湿度敏感的介电层，以在第一和第二电极之间形成中空区域。

公开(公告)号：US09025339B2

公开(公告)日：2015-05-05

申请号：US13340345

申请日：2011-12-29

Applicant: Jing-En Luan ,  Hk Looi

Inventor： Jing-En Luan ,  Hk Looi

IPC: H05K7/06 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34

CPC classification number: H05K3/305 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/09781 ,  H05K2201/09909 ,  Y02P70/613 ,  Y10T29/4913

Abstract: On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate.

Abstract translation: 在其上使用粘合剂将电子或结构部件耦合到基板的电路基板上，设置粘合剂阻挡层以防止粘合剂干扰电路的操作。 可以在选定的位置提供接触垫并具有选定的形状，并将焊料沉积在垫上，然后回流以形成坝。 大坝可以是焊接到接触垫的结构，或者可以通过设备的另一种结构在其端部处支撑坝，使得在其用于容纳粘合剂的位置处，该坝不附着到基底。

公开(公告)号：US09018753B2

公开(公告)日：2015-04-28

申请号：US13958146

申请日：2013-08-02

Applicant: STMicroelectronics Pte Ltd.

Inventor： Wing Shenq Wong

IPC: H01L23/12 ,  H01L23/22 ,  H01L23/24 ,  H01L23/04 ,  H01L21/82 ,  H01L23/00 ,  H01L21/10

CPC classification number: H01L23/04 ,  H01L21/10 ,  H01L21/82 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.

Abstract translation: 描述了一种用于制造电子模块的方法，包括将限定多个空腔的矩阵面板模制到基板上，将半导体管芯附着到模制矩阵面板的相应空腔中的基板面板，将半导体管芯电连接到基板面板， 模制矩阵面板的盖子以形成电子模块组件，将电子模块组件安装在载带上，以及将电子模块组件分离成各个电子模块。 描述了一种电子模块，其包括衬底，模制在衬底上的壁构件，限定空腔的模制壁构件，至少一个连接到空腔中的衬底并电连接到衬底的半导体管芯，以及固定到 模制的壁构件在空腔上。

公开(公告)号：US09018723B2

公开(公告)日：2015-04-28

申请号：US13929610

申请日：2013-06-27

Applicant: STMicroelectronics Pte Ltd

Inventor： Olivier Le Neel ,  Ravi Shankar ,  Tien Choy Loh

IPC: H01L31/0232 ,  H01L29/84 ,  H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14634 ,  H01L27/1467 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2924/1461

Abstract: The present disclosure is directed to an infrared sensor that includes a plurality of pairs of support structures positioned on the substrate, each pair including a first support structure adjacent to a second support structure. The sensor includes plurality of pixels, where each pixel is associated with one of the pairs of support structures. Each pixel includes a first infrared reflector layer on the substrate between the first and the second support structures, a membrane formed on the first and second support structures, a thermally conductive resistive layer on the membrane and positioned above the first infrared reflector layer, a second infrared reflector layer on the resistive layer, and an infrared absorption layer on the second infrared reflector layer.

Abstract translation: 本公开涉及一种红外传感器，其包括定位在基板上的多对支撑结构，每对包括邻近第二支撑结构的第一支撑结构。 传感器包括多个像素，其中每个像素与一对支撑结构中的一个相关联。 每个像素包括在第一和第二支撑结构之间的衬底上的第一红外反射器层，形成在第一和第二支撑结构上的膜，膜上的导热电阻层并且位于第一红外反射层之上，第二 电阻层上的红外线反射层，以及第二红外线反射层上的红外线吸收层。

公开(公告)号：US09018645B2

公开(公告)日：2015-04-28

申请号：US14013507

申请日：2013-08-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Yonggang Jin

IPC: H01L31/173 ,  H01L23/00

CPC classification number: H01L31/173 ,  H01L21/568 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L27/14678 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronics assembly includes a semiconductor die assembly, an enclosure affixed to the semiconductor die assembly, the enclosure defining first and second chambers over the semiconductor die assembly, and first and second optical elements mounted in the first and second chambers, respectively. The semiconductor die assembly includes a semiconductor die encapsulated in a molded material, an encapsulation layer located on the top surface of the semiconductor die, and at least one patterned metal layer and at least one dielectric layer over the encapsulation layer. Conductive pillars extend through the encapsulation layer for electrical connection to the semiconductor die. The encapsulation layer blocks optical crosstalk between the first and second chambers. A method is provided for making the electronics assembly.

Abstract translation: 电子组件包括半导体管芯组件，固定到半导体管芯组件的外壳，在半导体管芯组件上限定第一和第二腔室的外壳，以及安装在第一和第二腔室中的第一和第二光学元件。 半导体管芯组件包括封装在模制材料中的半导体管芯，位于半导体管芯的顶表面上的封装层，以及至少一个图案化金属层和封装层上的至少一个介电层。 导电柱延伸穿过封装层，以与半导体管芯电连接。 封装层阻止第一和第二腔室之间的光学串扰。 提供了一种用于制造电子组件的方法。

公开(公告)号：US08999446B2

公开(公告)日：2015-04-07

申请号：US13544865

申请日：2012-07-09

Applicant: Ying Yu ,  TienChoy Loh ,  ShianYeu Kam

Inventor： Ying Yu ,  TienChoy Loh ,  ShianYeu Kam

IPC: B05D3/10 ,  B05D5/02 ,  C03C17/32 ,  G01N33/487

CPC classification number: C03C17/32 ,  C03C15/00 ,  C03C2204/08 ,  G01N33/4875 ,  G01N2203/0091

Abstract: The present disclosure is directed to systems and methods for adjusting adhesion strength between materials during semiconductor sensor processing. One or more embodiments are directed to using various surface treatments to a substrate to adjust adhesion strength between the substrate and a polymer. In one embodiment, the surface of the substrate is roughened to decrease the adhesive strength between the substrate and the polymer. In another embodiment, the surface of the substrate is smoothed to increase the adhesive strength between the substrate and the polymer.

Abstract translation: 本发明涉及用于在半导体传感器处理期间调节材料之间的粘附强度的系统和方法。 一个或多个实施例涉及使用对基底的各种表面处理来调节基底和聚合物之间的粘合强度。 在一个实施方案中，基底的表面被粗糙化以降低基底和聚合物之间的粘合强度。 在另一个实施方案中，使基材的表面平滑以增加基材和聚合物之间的粘合强度。

公开(公告)号：US08987871B2

公开(公告)日：2015-03-24

申请号：US13485631

申请日：2012-05-31

Applicant: Jerome Teysseyre ,  Glenn de los Reyes ,  Wee Chin Judy Lim

Inventor： Jerome Teysseyre ,  Glenn de los Reyes ,  Wee Chin Judy Lim

IPC: H01L23/60 ,  H05K9/00

CPC classification number: H05K9/003

Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.

Abstract translation: 用于微机电系统装置的盖子包括第一层，例如其中形成有通孔的双马来酰亚胺三嗪（BT）树脂材料，层压到封闭第一层中的孔的第二层BT树脂材料上，形成 一个空腔。 第一层和第二层与热固性粘合剂层压，该热固性粘合剂足够厚以封装可以从用于形成孔的路由操作保留的颗粒。 空腔的内部，包括粘合剂的暴露部分和第一层的暴露表面涂覆有导电涂料。 使用导电粘合剂将盖子粘附到MEMS装置上的基板上，导电粘合剂将导电涂料层耦合到基板的接地平面。 导电涂料层用作屏蔽，以防止或减少作用在MEMS器件上的电磁干扰。

公开(公告)号：US08860207B2

公开(公告)日：2014-10-14

申请号：US14177146

申请日：2014-02-10

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics Grenoble 2 SAS

Inventor： Yonggang Jin ,  Romain Coffy ,  Jerome Teysseyre

IPC: H01L23/34 ,  H01L21/00 ,  H01R43/16 ,  H01L23/498 ,  H01L23/36 ,  H01L23/31 ,  H01L21/768

CPC classification number: H01L23/498 ,  H01L21/561 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/49124 ,  Y10T29/49174 ,  Y10T29/49204 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

公开(公告)号：US20140292344A1

公开(公告)日：2014-10-02

申请号：US13853666

申请日：2013-03-29

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Olivier Le Neel ,  Calvin Leung

IPC: G01R31/36

CPC classification number: G01R31/3679 ,  G01R31/3662 ,  H02J7/0006 ,  H02J7/0016 ,  H02J7/0021 ,  H02J7/0036

Abstract: A device is provided for monitoring the total current discharged from a battery. The device includes a bridge circuit of resistors in which one of the resistors has a resistance which varies according to the current which has passed through it. Whenever the battery passes a current to a load, a small portion of the current is passed through the bridge circuit.

Abstract translation: 提供了用于监测从电池释放的总电流的装置。 该装置包括电阻器的桥接电路，其中一个电阻器具有根据已经通过它的电流而变化的电阻。 每当电池通过电流到负载时，电流的一小部分通过桥接电路。

公开(公告)号：US08809861B2

公开(公告)日：2014-08-19

申请号：US12981375

申请日：2010-12-29

Applicant: Olivier Le Neel ,  Ravi Shankar ,  Calvin Leung

Inventor： Olivier Le Neel ,  Ravi Shankar ,  Calvin Leung

IPC: H01L29/786 ,  H01L49/00

CPC classification number: H01L49/00 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78684 ,  Y10S257/902

Abstract: A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device.

Abstract translation: 形成具有薄膜金属沟道区的晶体管。 晶体管可以形成在半导体衬底的表面，绝缘衬底或衬底之上的电介质层之间。 可以形成各自具有薄膜金属沟道区的多个晶体管。 这种晶体管的多个阵列可以垂直地堆叠在相同的器件中。