公开(公告)号：US20100233359A1

公开(公告)日：2010-09-16

申请号：US12782867

申请日：2010-05-19

Applicant: Takeshi SHIOGA ,  Masataka MIZUKOSHI ,  Kazuaki KURIHARA

Inventor： Takeshi SHIOGA ,  Masataka MIZUKOSHI ,  Kazuaki KURIHARA

IPC: H01G4/00

CPC classification number: H05K1/162 ,  H01G9/025 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract translation: 对于用于半导体集成电路元件的电极焊盘，用于信号传输的一些电极焊盘耦合到Ti膜。 用于信号传输的其他电极焊盘通过布线在多层布线中的布线耦合到电极焊盘。 用于电源的电极焊盘耦合到电极焊盘，电极彼此不同的电力线通过布线耦合到电极焊盘。 电极焊盘也耦合到铝箔（阳极）。 用于接地的电极焊盘耦合到接地线通过布线耦合到的电极焊盘。 电极焊盘也耦合到导电聚合物膜（阴极）。

公开(公告)号：US07755910B2

公开(公告)日：2010-07-13

申请号：US11882646

申请日：2007-08-03

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H05K1/16

CPC classification number: H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2224/16268 ,  H01L2224/81192 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H05K1/162 ,  H05K2201/0367 ,  H05K2201/09763 ,  H05K2201/10378 ,  Y10T29/435

Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

Abstract translation: 本发明的电容器内置插入件包括基底树脂层，设置成穿过基底树脂层并具有从基底树脂层的两个表面侧突出的突出部分的电容器第一电极，其中突出部分在一个 基础树脂层的表面侧用作连接部分，用于覆盖基础树脂层的另一表面侧上的第一电极的突出部分的电容器电介质层和用于覆盖电介质层的电容器第二电极，其中多个 每个由第一电极，电介质层和第二电极构成的电容器在电容器通过基础树脂层的状态下沿横向排列和排列。

公开(公告)号：US07682970B2

公开(公告)日：2010-03-23

申请号：US11478294

申请日：2006-06-29

Applicant: Constantine P. Grigoropoulos ,  Seung-Hwan Ko ,  Jaewon Chung ,  Dimos Poulikakos ,  Heng Pan

Inventor： Constantine P. Grigoropoulos ,  Seung-Hwan Ko ,  Jaewon Chung ,  Dimos Poulikakos ,  Heng Pan

IPC: H01L21/44

CPC classification number: H01L21/44 ,  H01L21/288 ,  H01L21/4867 ,  H01L21/76838 ,  H05K1/0393 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/027 ,  H05K3/1241 ,  H05K3/4685 ,  H05K2201/09763 ,  H05K2203/107 ,  H05K2203/1131 ,  Y10S438/94

Abstract: The present invention relates to systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Drop-on-demand systems are used in some embodiments to fabricate various electronic structures including conductors, capacitors, FETs. Selective laser ablation is used in some embodiments to pattern more precisely the circuit elements and to form small channel devices.

Abstract translation: 本发明涉及从纳米颗粒的悬浮液形成导电，半导电和电介质层，结构和器件的系统，材料和方法。 在一些实施例中使用点播系统来制造包括导体，电容器，FET的各种电子结构。 在一些实施例中使用选择性激光烧蚀来更精确地模拟电路元件并形成小通道器件。

公开(公告)号：US20090290316A1

公开(公告)日：2009-11-26

申请号：US11917418

申请日：2006-06-13

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H05K1/18

CPC classification number: H05K1/11 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A printed wiring board includes a mounting portion on which a dual core processor including two processor cores in a single chip can be mounted, power supply lines, ground lines, and a first layered capacitor and a second layered capacitor that are independently provided for each of the processor cores, respectively. Accordingly, even when the electric potentials of the processor cores instantaneously drop, an instantaneous drop of the electric potential can be suppressed by action of the layered capacitors corresponding to the processor cores, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

Abstract translation: 一种印刷线路板包括：安装部，在该安装部上可以搭载有单个芯片的两个处理器芯的双芯处理器，电源线，接地线以及第一分层电容器和第二分层电容器， 处理器核心。 因此，即使当处理器核心的电位瞬时下降时，也可以通过分别对应于处理器核心的分层电容器的作用来抑制电位的瞬时下降。 此外，即使处理器核心中的一个的电压变化，电压的变化也不影响其他的处理器核心，因此不会发生故障。

公开(公告)号：US07613007B2

公开(公告)日：2009-11-03

申请号：US11289994

申请日：2005-11-30

Applicant: Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  David Ross McGregor ,  Attiganal N. Sreeram

Inventor： Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  David Ross McGregor ,  Attiganal N. Sreeram

IPC: H05K1/18

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09763 ,  H01L2224/0401

Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

Abstract translation: 本发明涉及一种包括功率核心的器件，其中所述功率核心包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压体; 其中所述平面电容器层叠体用作低电感路径以向所述至少一个嵌入式分离电容器提供电荷; 并且其中所述至少一个嵌入式单电容器与所述平面电容器层压体中的至少一个并联连接; 并且其中所述功率核心与至少一个信号层相互连接。

公开(公告)号：US20090231820A1

公开(公告)日：2009-09-17

申请号：US12357867

申请日：2009-01-22

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/18 ,  H05K7/02 ,  H01G4/06 ,  H05K7/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/305 ,  H05K2201/0175 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10977

Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer, a first electrode and a second electrode, the high dielectric layer being interposed between the first and second electrodes. A plurality of resin insulating layers are formed on the insulating layer and include an upper resin insulating layer provided on a first electrode side of the capacitor, and a lower resin insulating layer provided on a second electrode side of the capacitor. A semiconductor device mounting pad includes a first pad and a second pad, the semiconductor device mounting pad being formed on an outermost resin insulating layer of the resin insulating layers, and a first via conductor is formed in at least one of the resin insulating layers to electrically connect the first pad with the first electrode. A second via conductor is formed in at least another one layer of the resin insulating layers to electrically connect the second pad with the second electrode, and an underfill covered area covered with an underfill resin is provided between the semiconductor device and the printed wiring board. The underfill covered area is provided on a surface of the printed wiring board facing the semiconductor device. When the underfill covered area is projected along a lamination direction of the resin insulating layers to a face on which the high dielectric layer is formed, the underfill covered area is larger than an area in which the high dielectric layer is formed. The capacitor is located under the underfill covered area.

Abstract translation: 印刷电路板包括绝缘层和包括陶瓷高介电层，第一电极和第二电极的电容器，高电介质层介于第一和第二电极之间。 在绝缘层上形成多个树脂绝缘层，并且包括设置在电容器的第一电极侧的上部树脂绝缘层和设置在电容器的第二电极侧的下部树脂绝缘层。 半导体器件安装焊盘包括第一焊盘和第二焊盘，半导体器件安装焊盘形成在树脂绝缘层的最外层树脂绝缘层上，第一通孔导体形成在至少一个树脂绝缘层中， 将第一焊盘与第一电极电连接。 第二通孔导体形成在至少另一层树脂绝缘层中，以将第二焊盘与第二电极电连接，并且在半导体器件和印刷线路板之间设置由底部填充树脂覆盖的底部填充覆盖区域。 底部填充覆盖区域设置在面向半导体器件的印刷线路板的表面上。 当底层填充覆盖区域沿着树脂绝缘层的层叠方向投影到形成有高介电层的面时，底部填充覆盖面积大于其中形成高介电层的面积。 电容器位于底部填充覆盖区域下方。

公开(公告)号：US07586198B2

公开(公告)日：2009-09-08

申请号：US11321934

申请日：2005-12-29

Applicant: William J. Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Matthew C. Snogren ,  Richard H. Snogren

Inventor： William J. Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Matthew C. Snogren ,  Richard H. Snogren

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/4679 ,  H01L2224/16225 ,  H05K1/0269 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09063 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/0338 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49146 ,  Y10T29/49156

Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.

Abstract translation: 内层板在制造过程中提供高密度基准。 可以使用X射线识别基准，而不蚀刻掉内层面板的部分以暴露基准。

公开(公告)号：US20090139756A1

公开(公告)日：2009-06-04

申请号：US12168274

申请日：2008-07-07

Applicant: Ying-Ming Lee

Inventor： Ying-Ming Lee

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/28 ,  H05K3/385 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/095 ,  Y10T29/4913

Abstract: A fabricating process of a circuit board with an embedded passive component is described. First, a conductive layer including a first surface and a second surface opposite thereto is provided. The first surface has at least one component region on which at least one passive component material layer is formed. A passivation layer is formed on the first surface to cover the passive component material layer. A brown oxidation process is performed on the conductive layer. A circuit unit and an insulation layer are provided, and the insulation layer is set between the circuit unit and the conductive layer. The conductive layer, the circuit unit and the insulation layer are laminated. The passive component material layer is between the insulation layer and the conductive layer. The conductive layer is patterned to form a circuit layer.

Abstract translation: 描述具有嵌入式无源元件的电路板的制造工艺。 首先，提供包括第一表面和与其相对的第二表面的导电层。 第一表面具有至少一个组分区域，在其上形成至少一个无源组分材料层。 钝化层形成在第一表面上以覆盖被动元件材料层。 在导电层上进行棕色氧化处理。 设置电路单元和绝缘层，并且将绝缘层设置在电路单元和导电层之间。 导电层，电路单元和绝缘层被层压。 无源部件材料层位于绝缘层和导电层之间。 将导电层图案化以形成电路层。

公开(公告)号：US20090097218A1

公开(公告)日：2009-04-16

申请号：US12285447

申请日：2008-10-06

Applicant: Garo Miyamoto

Inventor： Garo Miyamoto

IPC: H05K1/16 ,  H05K13/00

CPC classification number: H05K1/162 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09763 ,  Y10T29/49172

Abstract: There is provided a capacitor-embedded printed wiring board incorporating therein a capacitor having stabilized electrical characteristics. The capacitor-embedded printed wiring board includes: a capacitor having a first electrode 5, a high dielectric constant layer 7 and a second electrode 9 which are sequentially laminated on an insulating substrate 1, the second electrode being electrically connected to a land 6 for electrode contact formed in a wiring layer in which the first electrode is formed; a member 12 having at least one insulating layer and laminated over the capacitor and the wiring layer; and a via 18 having an opening extending through the member and the second electrode to reach the land, the via electrically interconnecting the second electrode and the land in the opening. A method of manufacturing the same is also provided.

Abstract translation: 提供了一种电容器嵌入式印刷线路板，其中结合有具有稳定的电特性的电容器。 电容器嵌入式印刷电路板包括：电容器，其具有依次层叠在绝缘基板1上的第一电极5，高介电常数层7和第二电极9，第二电极电连接到电极用焊盘6 形成在其中形成第一电极的布线层中的接触; 具有至少一个绝缘层并层压在电容器和布线层上的构件12; 以及通孔18，其具有延伸穿过所述构件的开口和所述第二电极到达所述平台，所述通孔将所述第二电极和所述开口中的所述平台电连接。 还提供了一种制造该方法的方法。

公开(公告)号：US20090079074A1

公开(公告)日：2009-03-26

申请号：US12232008

申请日：2008-09-09

Applicant: Kazuhiro Motonaga

Inventor： Kazuhiro Motonaga

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposing to the first surface, a semiconductor chip mounted on the first surface of the substrate, a first pad formed on the first surface of the substrate to electrically connect to a first terminal of the semiconductor chip, a second pad formed on the second surface of the substrate to electrically connect to a second terminal of the semiconductor chip, and a decoupling capacitor formed on the first surface and including the first and second pads serving as electrodes of the decoupling capacitor.

Abstract translation: 一种半导体器件，包括具有第一表面和与第一表面相对的第二表面的衬底，安装在衬底的第一表面上的半导体芯片，形成在衬底的第一表面上的第一焊盘，以电连接到第一端子 所述第二焊盘形成在所述衬底的所述第二表面上以电连接到所述半导体芯片的第二端子，以及形成在所述第一表面上并且包括用作所述解耦的电极的所述第一和第二焊盘的去耦电容器 电容器。