公开(公告)号：US09893719B2

公开(公告)日：2018-02-13

申请号：US14669670

申请日：2015-03-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/037 ,  H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  G11C11/24 ,  G11C14/00 ,  H01L27/06 ,  H01L27/105 ,  H03K19/173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

公开(公告)号：US09842842B2

公开(公告)日：2017-12-12

申请号：US14659714

申请日：2015-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L27/108 ,  H01L29/786 ,  G11C11/403

CPC classification number: H01L27/10897 ,  G11C11/403 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/1225 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V.

公开(公告)号：US09780093B2

公开(公告)日：2017-10-03

申请号：US14162837

申请日：2014-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L27/105 ,  H01L27/06 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156

CPC classification number: H01L27/1052 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

公开(公告)号：US09728243B2

公开(公告)日：2017-08-08

申请号：US15149291

申请日：2016-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: G11C11/24 ,  G11C5/02 ,  H01L29/786 ,  H01L27/12 ,  G11C11/4091 ,  H01L23/522 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/56 ,  H01L27/108 ,  G11C7/14

CPC classification number: G11C11/24 ,  G11C5/025 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/56 ,  G11C11/565 ,  H01L23/5223 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

公开(公告)号：US09672873B2

公开(公告)日：2017-06-06

申请号：US15159919

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Kiyoshi Kato

IPC: G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  G11C8/16 ,  G11C11/405 ,  G11C11/408 ,  G11C11/56 ,  H01L27/12 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/24 ,  G11C11/409 ,  H01L23/528 ,  H01L27/105 ,  H01L29/24 ,  H01L27/1156

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

公开(公告)号：US09542977B2

公开(公告)日：2017-01-10

申请号：US14681570

申请日：2015-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka ,  Yuto Yakubo

IPC: G11C5/02 ,  H01L29/24 ,  H01L27/12 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

公开(公告)号：US09489988B2

公开(公告)日：2016-11-08

申请号：US15041435

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Takanori Matsuzaki

IPC: G11C5/10

CPC classification number: G11C5/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/565 ,  G11C2207/101 ,  G11C2207/108 ,  H01L27/1156

Abstract: To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to fourth capacitors, first to fourth nodes, and first and second wirings. The first node is connected to the first capacitor and a gate of the first transistor, the second node is connected to the second capacitor and a gate of the second transistor, the third node is connected to the third capacitor and a gate of the third transistor, and the fourth node is connected to the fourth capacitor and a gate of the fourth transistor. Multiple pieces of multilevel data is written to the first to fourth nodes through the second to fifth transistors. The second to fifth transistors each preferably include an oxide semiconductor in a channel formation region.

Abstract translation: 提供可以写入和读取多个多级数据的存储器件。 存储器件包括第一至第五晶体管，第一至第四电容器，第一至第四节点以及第一和第二布线。 第一节点连接到第一电容器和第一晶体管的栅极，第二节点连接到第二电容器和第二晶体管的栅极，第三节点连接到第三电容器和第三晶体管的栅极 并且第四节点连接到第四电容器和第四晶体管的栅极。 多个多电平数据通过第二至第五晶体管写入第一至第四节点。 第二至第五晶体管各自优选地包括沟道形成区域中的氧化物半导体。

公开(公告)号：US09443592B2

公开(公告)日：2016-09-13

申请号：US14330481

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yasuhiko Takemura ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Shunpei Yamazaki

IPC: H01L21/00 ,  G11C16/04 ,  G11C16/20 ,  H01L21/28 ,  H01L27/108 ,  H01L27/115

CPC classification number: G11C16/0466 ,  G11C16/20 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11568

Abstract: A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.

Abstract translation: 提供了其中校正阈值的半导体器件的制造方法。 在包括多个晶体管的半导体器件中，每个包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在电荷陷阱层 通过进行热处理，同时保持栅电极的电位高于源电极或漏电极的电位1秒以上。 通过该过程，阈值增加并且Icut减小。 用于向栅电极提供信号的电路和用于向源电极或漏电极提供信号的电路彼此电分离。 该处理在前一电路的电位被设置为高于后一电路的电位的状态下执行。

公开(公告)号：US09443564B2

公开(公告)日：2016-09-13

申请号：US14993375

申请日：2016-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Wataru Uesugi ,  Kiyoshi Kato ,  Tatsuya Onuki

IPC: G11C5/14 ,  G11C14/00

CPC classification number: G11C11/419 ,  G06F2212/221 ,  G11C5/14 ,  G11C5/148 ,  G11C11/418 ,  G11C14/0054 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract translation: 提供具有新颖结构的半导体器件。 提供一种降低功耗的半导体器件。 包括能够将数据备份到非易失性存储器的SRAM和存储器单元的外围电路的存储单元被配置为提供不同的功率门控状态。 在非常短的第一时段中，通过关闭开关使位线进入电浮动状态。 在比第一期间长的第二期间，对存储单元进行电力门控。 在比第二时段长的第三时段中，对存储单元和外围电路进行功率门控。

公开(公告)号：US09412739B2

公开(公告)日：2016-08-09

申请号：US14682476

申请日：2015-04-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/786 ,  H01L21/8258 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/7869

Abstract: A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor provided over the first insulator so as to overlap with the first conductor, a second insulator over the oxide semiconductor, a second conductor over the second insulator, and a third conductor and a fourth conductor in contact with the oxide semiconductor. The oxide semiconductor includes a region overlapping with the first region and not overlapping with the second region, and a region not overlapping with the first conductor and overlapping with the second conductor in a region positioned between the third conductor and the fourth conductor when viewed from above. The second transistor is a p-channel transistor. A layer in which the first transistor is provided and a layer in which the second transistor is provided are stacked together.

Abstract translation: 提供了减小面积的半导体。 第一晶体管包括第一导体，第一导体上的第一绝缘体，设置在第一绝缘体上以与第一导体重叠的氧化物半导体，氧化物半导体上的第二绝缘体，第二绝缘体上的第二导体，以及 与氧化物半导体接触的第三导体和第四导体。 氧化物半导体包括与第一区域重叠并且不与第二区域重叠的区域，以及当从上方观察时，位于第三导体和第四导体之间的区域中与第一导体不重叠并与第二导体重叠的区域 。 第二晶体管是p沟道晶体管。 提供第一晶体管的层和设置第二晶体管的层堆叠在一起。