公开(公告)号：US09523815B2

公开(公告)日：2016-12-20

申请号：US14638292

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Estelle Batail

IPC: G02B6/42 ,  G02B6/122 ,  H01L29/74 ,  H01L27/02

CPC classification number: G02B6/122 ,  G02B6/4275 ,  G02B6/4295 ,  H01L27/0248 ,  H01L29/74

Abstract: A thyristor may include a first optical waveguide segment in a semiconductor material, having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. The thyristor may further include a second optical waveguide segment in a semiconductor material, adjacent the first waveguide segment and having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. A transverse bipolar junction may be between the second longitudinal portions of the first and second waveguide segments. An electrical insulator may separate each of the first longitudinal portions from the waveguide segment adjacent thereto.

Abstract translation: 晶闸管可以包括半导体材料中的第一光波导段，其具有构造为在其间形成纵向双极结的相反导电类型的第一和第二互补纵向部分。 晶闸管可以进一步包括半导体材料中的第二光波导段，邻近第一波导段并且具有构造成在其间形成纵向双极结的相反导电类型的第一和第二互补纵向部分。 横向双极结可以在第一和第二波导段的第二纵向部分之间。 电绝缘体可以将每个第一纵向部分与与其相邻的波导段分开。

公开(公告)号：US09520435B2

公开(公告)日：2016-12-13

申请号：US14840665

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Nayera Ahmed ,  Michel Marty

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor including a semiconductor layer; a stack of insulating layers resting on the back side of the semiconductor layer; a conductive layer portion extending along part of the height of the stack and flush with the exposed surface of the stack; laterally-insulated conductive fingers extending through the semiconductor layer from its front side and penetrating into said layer portion; laterally-insulated conductive walls separating pixel areas, these walls extending through the semiconductor layer from its front side and having a lower height than the fingers; and an interconnection structure resting on the front side of the semiconductor layer and including vias in contact with the fingers.

Abstract translation: 包括半导体层的图像传感器; 沉积在半导体层的背面上的一叠绝缘层; 导电层部分，其沿所述堆叠的高度的一部分延伸并与所述堆叠的暴露表面齐平; 横向绝缘的导电指状物从其前侧延伸穿过半导体层并且穿透到所述层部分中; 分隔像素区域的横向绝缘导电壁，这些壁从其前侧延伸穿过半导体层并且具有比手指低的高度; 以及搁置在半导体层的前侧上并且包括与手指接触的通孔的互连结构。

公开(公告)号：US20160343720A1

公开(公告)日：2016-11-24

申请号：US14952662

申请日：2015-11-25

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

Abstract translation: 集成电路包括具有位于掩埋绝缘层上方的半导体膜的绝缘体上硅衬底。 一次可编程类型的至少一个存储单元包括具有第一电极区域的MOS电容器，该第一电极区域包括至少部分硅化并且侧壁为绝缘横向区域的栅极区域，位于栅极区域和半导体膜之间的电介质层 以及包括半导体膜的硅化物区域的第二电极区域，位于绝缘横向区域旁边并且至少部分地延伸到介电层下方。

公开(公告)号：US20160307640A1

公开(公告)日：2016-10-20

申请号：US14956963

申请日：2015-12-02

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Antoine Benoist ,  Stephane Denorme ,  Joel Damiens

IPC: G11C17/16 ,  G11C17/18

CPC classification number: G11C17/165 ,  G11C5/145 ,  G11C5/147 ,  G11C7/04 ,  G11C17/16 ,  G11C17/18

Abstract: A memory cell of the one-time-programmable type is programmed by application of a programming voltage having a value sufficient to obtain a breakdown of a dielectric of a capacitor within the cell. A programming circuit generates the programming voltage as a variable voltage that varies as a function of a temperature (T) of the cell. In particular, the programming voltage varies based on a variation law decreasing as a function of the temperature.

Abstract translation: 通过施加具有足以获得电池内的电容器的电介质的击穿的编程电压来编程一次性可编程类型的存储单元。 编程电路产生编程电压作为可变电压，其随电池的温度（T）而变化）。 特别地，编程电压根据作为温度的函数的变化规律减小而变化。

公开(公告)号：US09453977B2

公开(公告)日：2016-09-27

申请号：US15140701

申请日：2016-04-28

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122 ,  H01L23/528 ,  H01L25/16 ,  H01L27/02 ,  H01L29/87 ,  H01L23/498

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护芯片中的第一芯片的元件的至少一个部件形成在第二芯片中。 优选地，芯片是SOI型的，第二芯片包括具有足以支撑用于保护元件的部件的第一厚度的SOI层。 第一芯片还包括SOI层，但是具有小于不足以支撑用于保护元件的部件的第一厚度的第二厚度。 第二芯片的SOI层可以是光波导层。

公开(公告)号：US20160266415A1

公开(公告)日：2016-09-15

申请号：US15163178

申请日：2016-05-24

Applicant: STMICROELECTRONICS SA

Inventor： JEAN-ROBERT MANOUVRIER

IPC: G02F1/01 ,  G02F1/225 ,  G02F1/025 ,  G01J9/00 ,  G01J9/02

CPC classification number: G02F1/0123 ,  G01J9/00 ,  G01J9/02 ,  G02F1/025 ,  G02F1/218 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/58 ,  G02F2203/50 ,  H04B10/5053 ,  H04B10/50575

Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.

Abstract translation: 光调制器使用光电相位比较器，其被配置为以电信号的形式提供两个光波之间的相位差的量度。 相位比较器包括具有两个耦合通道的光学定向耦合器，该耦合通道分别限定用于接收要比较的两个光波的两个光学输入。 两个光电二极管被配置为分别接收定向耦合器的两个通道的光输出功率。 电路被配置为提供与两个光电二极管产生的电信号之间的差成比例的电信号作为光相移的测量。

公开(公告)号：US09418954B2

公开(公告)日：2016-08-16

申请号：US14659680

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/3213 ,  H01L21/56 ,  H01L21/768 ,  H01L23/36 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract translation: 一种装置包括组装在插入器上的芯片。 电绝缘层在芯片周围涂覆插入件的上表面。 第一金属线在插入件的上表面上延伸并且布置在与芯片连接的导电元件之间。 每个第一金属线的端部被布置成延伸超过芯片在插入件上的投影。 导热通孔将第一金属线的端部连接到支撑在设备的上表面处的散热器。

公开(公告)号：US09418313B2

公开(公告)日：2016-08-16

申请号：US14452761

申请日：2014-08-06

Applicant: STMicroelectronics SA

Inventor： Stéphane Valente

IPC: G06K9/62 ,  G06K9/46

CPC classification number: G06K9/6202 ,  G06K9/46 ,  G06K9/4671 ,  G06K2009/4666 ,  G06K2009/6213

Abstract: A method for extracting characteristic points from an image, includes extracting characteristic points from a first image, generating for each characteristic point a descriptor with several components describing an image region around the characteristic point, and comparing two by two the descriptors of the first image, the characteristic points whose descriptors have a proximity between them greater than an ambiguity threshold, being considered ambiguous.

Abstract translation: 一种用于从图像中提取特征点的方法，包括从第一图像中提取特征点，为每个特征点生成描述符包含描述特征点周围的图像区域的描述符的描述符，并且将第二图像的描述符比较两个， 其描述符之间的接近度大于歧义阈值的特征点被认为是不明确的。

公开(公告)号：US20160233641A1

公开(公告)日：2016-08-11

申请号：US14945859

申请日：2015-11-19

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain CHANTRE ,  Charles BAUDOT ,  Sébastien CREMER

IPC: H01S5/026 ,  H01S5/22 ,  H01S5/125

CPC classification number: H01S5/026 ,  G02B6/12004 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/136 ,  H01S5/021 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0267 ,  H01S5/0268 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/0656 ,  H01S5/1032 ,  H01S5/1035 ,  H01S5/125 ,  H01S5/22 ,  H01S5/2206

Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

Abstract translation: 光子集成电路包括封装至少一个金属化水平的第一绝缘区域，至少部分地封装激光源的增益介质的第二绝缘区域和放置在两个绝缘区域之间的层叠结构。 层叠结构包括第一多晶或单晶硅层，第二多晶或单晶硅层，与激光源的波长光学兼容并且可相对于硅选择性地蚀刻的中间层，并且将第一层与 所述第二层的第一部分和所述增益介质面向所述第一层的至少一部分。 第一层，中间层和第二层的第一部分形成包含谐振腔和波导的组件，光学耦合到增益介质，第二层的第二部分包含至少一个其他光子 零件。

公开(公告)号：US09406372B2

公开(公告)日：2016-08-02

申请号：US13836690

申请日：2013-03-15

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.