公开(公告)号：US20140377910A1

公开(公告)日：2014-12-25

申请号：US14478799

申请日：2014-09-05

Applicant: STMicroelectronics, Inc.

Inventor： Jerry Tan ,  William Cabreros

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/4828 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48471 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of bond pads, none of which extend as far as a lateral face of the body. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and bond pads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and bond pads, back surfaces of which remain exposed at a back face of the body. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of bond pads on one side of the substrate and a plurality of cavities on the opposite face.

Abstract translation: 无引线半导体封装包括在引线框上的封装体，其包括管芯焊盘和多个接合焊盘，其中没有一个延伸到主体的侧面。 在包装的制造期间，将模塑料沉积在引线框的面上，在其上定位有管芯焊盘和焊盘。 在模塑料固化之后，对引线框架的背面进行蚀刻以隔离模板和粘结垫，焊盘的背面在主体的背面保持暴露。 在引线框的制造期间，蚀刻母基板以限定管芯焊盘和在衬底的一侧上的多个接合焊盘和在相对的面上的多个空腔。

公开(公告)号：US08913607B2

公开(公告)日：2014-12-16

申请号：US13739857

申请日：2013-01-11

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l.

Inventor： Liwen Chu ,  George Vlantis ,  Vincenzo Scarpa

IPC: H04L12/28 ,  H04L12/50 ,  H04W84/18 ,  H04W72/12 ,  H04W84/12 ,  H04W84/22

CPC classification number: H04W48/14 ,  H04W40/34 ,  H04W48/08 ,  H04W72/02 ,  H04W72/1252 ,  H04W84/12 ,  H04W84/18 ,  H04W84/22 ,  Y02D70/142 ,  Y02D70/22

Abstract: The addition of high throughput capability elements to beacon frames and peer link action frames in wireless mesh networks enable the utilization of desirable features without further modifications to the network. Rules can be established for high throughput mesh point protection in a mesh network, Space-time Block Code (STBC) operations and 20/40 MHz operation selections. However, features such as PSMP (power save multi-poll) and PCO (phased coexistence operations) are barred from implementation to prevent collisions.

Abstract translation: 在无线网状网络中向信标帧和对等链路动作帧添加高吞吐量能力元素使得能够利用所需特征而无需进一步修改网络。 可以为网格网络中的高吞吐量网格点保护，空时块代码（STBC）操作和20/40 MHz操作选择建立规则。 然而，PSMP（省电多轮询）和PCO（分阶段共存操作）等功能被禁止实施以防止冲突。

公开(公告)号：US08907427B2

公开(公告)日：2014-12-09

申请号：US13668376

申请日：2012-11-05

Applicant: STMicroelectronics, Inc

Inventor： John H Zhang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/7833

Abstract: A semiconductor device may include a substrate, source and drain regions in the substrate, a recessed epitaxial channel layer in the substrate between the source and drain regions, and a high-K gate dielectric layer overlying the recessed epitaxial channel layer. The semiconductor device may further include a gate electrode overlying the high-K gate dielectric layer, a dielectric cap layer in contact with top and sidewall portions of the gate electrode, the dielectric cap layer having a lower dielectric constant than the high-K gate dielectric layer, and source and drain contacts coupled to the source and drain regions.

Abstract translation: 半导体器件可以包括衬底，衬底中的源极和漏极区域，在源极和漏极区域之间的衬底中的凹陷的外延沟道层以及覆盖凹陷的外延沟道层的高K栅极电介质层。 半导体器件还可以包括覆盖高K栅极电介质层的栅电极，与栅电极的顶部和侧壁部分接触的电介质盖层，介电覆盖层具有比高K栅极电介质低的介电常数 层，以及耦合到源极和漏极区域的源极和漏极接触。

公开(公告)号：US20140353767A1

公开(公告)日：2014-12-04

申请号：US13906505

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Balasubramanian Pranatharthiharan

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

公开(公告)号：US20140353760A1

公开(公告)日：2014-12-04

申请号：US13907613

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract translation: 描述了用于在体基板上将诸如Si和SiGe的两种半导体材料类型的finFET共集成的方法。 用于finFET的鳍可以形成在第一半导体类型的外延层中，并被绝缘体覆盖。 可以去除一部分翅片以在绝缘体中形成空隙，并且可以通过在空隙中外延生长第二类型的半导体材料来填充空隙。 共同集成的finFET可以形成在相同的器件级。

公开(公告)号：US20140353722A1

公开(公告)日：2014-12-04

申请号：US13907752

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Cindy Goldberg ,  Walter Kleemeier

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.

Abstract translation: 公开了石墨烯封盖HEMT器件及其制造方法。 石墨烯封盖的HEMT器件包括一个或多个石墨烯帽，其增强用于高频，高能量应用（例如无线电信）中的示例性AlGaN / GaN异质结构晶体管的器件性能和/或可靠性。 所公开的HEMT装置利用石墨烯的非凡材料特性。 其中一个石墨烯帽作为晶体管下面的散热器，而另一个石墨烯帽稳定晶体管的源极，漏极和栅极区域，以防止在大功率操作期间的开裂。 公开了一种工艺流程，用于用原子厚的石墨烯层替代先前用于防止裂纹的三层膜堆，而不会使装置性能降低。 此外，所公开的HEMT器件包括六边形氮化硼粘附层，以便于将复合氮化物半导体沉积到石墨烯上。

公开(公告)号：US20140353716A1

公开(公告)日：2014-12-04

申请号：US13906789

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成翅片掩模层，在鳍掩模层上形成虚拟栅极，以及在虚拟栅极的相对侧上形成源极和漏极区域。 去除虚拟栅极并且使用底层翅片掩模层来在半导体层中限定多个散热片。 在多个翅片上形成闸门。

公开(公告)号：US20140345517A1

公开(公告)日：2014-11-27

申请号：US13901298

申请日：2013-05-23

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: C30B23/04 ,  G02B6/13 ,  G02B6/12 ,  C30B25/04 ,  C30B29/06

CPC classification number: G02B6/107 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/032 ,  G02B6/122 ,  G02B6/131 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract translation: 在非牺牲半导体材料衬底层的顶部上形成牺牲半导体材料条。 外延生长非牺牲半导体材料的保形层以覆盖基底层和牺牲半导体材料条。 执行蚀刻以选择性地去除牺牲半导体材料条并留下被保形层和基底层包围的中空通道。 使用退火，共形层和基底层被回流以产生包括中空通道的光波导结构。

公开(公告)号：US20140340452A1

公开(公告)日：2014-11-20

申请号：US13893472

申请日：2013-05-14

Applicant: STMICROELECTRONICS ASIA PACIFIC PTE. LTD. ,  STMICROELECTRONICS PTE. LTD. ,  STMICROELECTRONICS, INC.

Inventor： Madanagopal Kunnavakkam ,  Jin Zhi Li ,  Teck Khim Neo ,  Kenneth W. Smiley ,  Chun Chek Bong

IPC: B41J2/14

CPC classification number: B41J2/14129 ,  B41J2/14072 ,  B41J2002/14387

Abstract: An ink jet printhead device includes a substrate and a plurality of thermal resistors on the substrate. Each thermal resistor includes first and second electrodes and a resistive layer extending therebetween. A polarity-changing driver is coupled to the plurality of thermal resistors and configured to change a driving polarity between the first and second electrodes of each of the plurality of thermal resistors.

Abstract translation: 喷墨打印头装置包括基板和基板上的多个热电阻器。 每个热敏电阻器包括第一和第二电极以及在它们之间延伸的电阻层。 极性改变驱动器耦合到多个热电阻器并且被配置为改变多个热电阻器中的每一个的第一和第二电极之间的驱动极性。

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。