公开(公告)号：US4829243A

公开(公告)日：1989-05-09

申请号：US157780

申请日：1988-02-19

Applicant: Ollie C. Woodard, Sr. ,  Andrew W. Ross

Inventor： Ollie C. Woodard, Sr. ,  Andrew W. Ross

IPC: G01Q60/00 ,  G01R31/305 ,  H01J37/04 ,  H01J37/244

CPC classification number: H01J37/045 ,  G01R31/305 ,  H01J2237/24507

Abstract: An electron beam testing apparatus for applying an electron beam to parts of an electronic component and measuring the secondary electrons released from the part including a secondary electron collector having a plurality of vertically extending screens with a detector positioned adjacent one of the screens. A different voltage is applied to each of the screens of the collector for collecting the secondary electrons over a large area. The apparatus may include a combination blanking and Faraday cup for metering the electron beam current when it is blanked. The apparatus may also be used to measure net work capacitance by measuring the time required to charge a network to a predetermined voltage.

公开(公告)号：US4810332A

公开(公告)日：1989-03-07

申请号：US222486

申请日：1988-07-21

Applicant: Ju-Don T. Pan

Inventor： Ju-Don T. Pan

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46 ,  C25D5/02

CPC classification number: H01L21/4857 ,  H01L23/49866 ,  H05K3/4647 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/096 ,  H05K2203/0577 ,  H05K2203/0585 ,  H05K2203/0733 ,  H05K3/108 ,  H05K3/243 ,  H05K3/388

Abstract: A method of making an electrical multilayer copper interconnect in which the electrical lines are protected by an electroplated overcoat. A plating interconnect is deposited on a substrate, a sacrificial layer of dielectric material is deposited on the plating interconnect. Thereafter a plating mask is formed on the dielectric material. Two self-aligned plating masks are patterned in one step, one of which is a plating mask for copper plating and the other is a plating mask for the overcoat. Preferably, before electroplating the overcoat, the copper is etched for exposing the sides adjacent the dielectric layer for allowing overcoating all of the copper.

Abstract translation: 一种制造电气多层铜互连的方法，其中电线被电镀的外涂层保护。 电镀互连沉积在衬底上，电介质材料的牺牲层沉积在电镀互连上。 此后，在电介质材料上形成电镀掩模。 两个自对准电镀掩模在一个步骤中被图案化，其中一个是用于镀铜的电镀掩模，另一个是用于外涂层的电镀掩模。 优选地，在电镀外涂层之前，蚀刻铜以暴露邻近介电层的侧面，以允许外涂全部铜。

公开(公告)号：US4776509A

公开(公告)日：1988-10-11

申请号：US52652

申请日：1987-05-19

Applicant: Gregory E. Pitts ,  David E. Boone ,  Daniel M. Andrews

Inventor： Gregory E. Pitts ,  David E. Boone ,  Daniel M. Andrews

IPC: B23K20/10 ,  B23K31/02

CPC classification number: H01L24/78 ,  B23K20/106 ,  H01L2224/78302 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30107

Abstract: A single point bonding apparatus and method for bonding one electrical conductor to a second electrical conductor by a thermosonic process using force, time, temperature and ultrasonic energy as the key parameters in forming the bonds. A bonding tool has a tip with a multiple of nonparallel surfaces extending from the end of the tip for maximizing the amount of ultrasonic energy coupled to the electrical conductors. The surfaces may be recessed into the end of the tip or protrude outwardly from the end of the tip for coupling ultrasonic energy in directions both parallel and perpendicular to the conductors.

Abstract translation: 一种单点接合装置和方法，用于通过使用力，时间，温度和超声波能量的热力过程将一个电导体连接到第二电导体作为形成键的关键参数。 接合工具具有从尖端的端部延伸的多个不平行表面的尖端，用于最大化耦合到电导体的超声能量的量。 表面可以凹入尖端的端部或从尖端的外部向外突出，用于在与导体平行和垂直的方向上耦合超声波能量。

公开(公告)号：US4681666A

公开(公告)日：1987-07-21

申请号：US930167

申请日：1986-11-13

Applicant: Curtis N. Potter ,  Harry Kroger

Inventor： Curtis N. Potter ,  Harry Kroger

IPC: C25D11/04 ,  H01L21/316 ,  H01L21/768 ,  C25D5/02

CPC classification number: H01L21/31687 ,  C25D11/022 ,  C25D11/04 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76888

Abstract: A planarization method of fabricating a layer of metal conductors embedded in a dielectric level. A coating of aluminum is anodized from the top but leaving a thickness of unanodized aluminum on the bottom. The top is masked and etched to provide a predetermined bare area which is etched out down to the unanodized aluminum. A metal is plated to the unanodized aluminum equal to the thickness of the unexposed anodic aluminum. The mask is removed and the unanodized aluminum is anodized. Therefore, the layer of metal and the dielectric anodic aluminum are planarized. Another anodizable metal may be used as an undercoat layer for completing the anodizing of the aluminum.

Abstract translation: 制造嵌入介电层的金属导体层的平面化方法。 从顶部阳极氧化铝的涂层，但在底部留下一定量的未阳极化的铝。 顶部被掩模和蚀刻以提供预定的裸露区域，其被蚀刻到未阳模化的铝。 将金属镀到等于未曝光的阳极铝的厚度的未阳极化的铝。 除去掩模，阳极氧化未阳极氧化的铝。 因此，金属层和介电阳极铝平坦化。 可以使用另一种阳极氧化金属作为底涂层，以完成铝的阳极氧化。

公开(公告)号：US5612712A

公开(公告)日：1997-03-18

申请号：US479270

申请日：1995-06-07

Applicant: Nalin Kumar ,  Chenggang Xie

Inventor： Nalin Kumar ,  Chenggang Xie

IPC: G09G3/22 ,  G09G3/30 ,  H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J29/08 ,  H01J29/28 ,  H01J31/12 ,  H01J61/067 ,  H01J63/06

CPC classification number: H01J1/304 ,  G09G3/22 ,  H01J1/3042 ,  H01J29/085 ,  H01J31/127 ,  H01J61/0677 ,  H01J63/06 ,  H01J9/027 ,  H01J2201/304 ,  H01J2201/30426 ,  H01J2201/30457 ,  H01J2201/319 ,  H01J2329/8625 ,  H01J2329/864

Abstract: A matrix-addressed diode flat panel display of field emission type is described, utilizing a diode (two terminal) pixel structure. The flat panel display comprises a cathode assembly having a plurality of cathodes, each cathode including a layer of cathode conductive material and a layer of a low effective work-function material deposited over the cathode conductive material and an anode assembly having a plurality of anodes, each anode including a layer of anode conductive material and a layer of cathodoluminescent material deposited over the anode conductive material, the anode assembly located proximate the cathode assembly to thereby receive charged particle emissions from the cathode assembly, the cathodoluminescent material emitting light in response to the charged particle emissions. The flat panel display further comprises means for selectively varying field emission between the plurality of corresponding light-emitting anodes and field-emission cathodes to thereby effect an addressable grey-scale operation of the flat panel display.

Abstract translation: 利用二极管（二端）像素结构描述场发射型矩阵寻址二极管平板显示器。 平板显示器包括具有多个阴极的阴极组件，每个阴极包括阴极导电材料层和沉积在阴极导电材料上的低有效功函数材料层和具有多个阳极的阳极组件， 每个阳极包括阳极导电材料层和沉积在阳极导电材料上的阴极发光材料层，阳极组件位于阴极组件附近，从而接收来自阴极组件的带电粒子发射，阴极发光材料响应于 带电粒子排放。 平板显示器还包括用于选择性地改变多个对应的发光阳极和场发射阴极之间的场发射的装置，从而实现平板显示器的可寻址的灰度级操作。

公开(公告)号：US5531880A

公开(公告)日：1996-07-02

申请号：US304918

申请日：1994-09-13

Applicant: Chenggang Xie ,  Donald E. Patterson ,  Nalin Kumar

Inventor： Chenggang Xie ,  Donald E. Patterson ,  Nalin Kumar

IPC: C25D13/02

CPC classification number: C25D13/02

Abstract: A system and method for producing thin, uniform powder phosphors for field emission display screens wherein a planarization of the phosphor powder layer is accomplished by placing the deposited phosphor layer in an anode plate between two optical flats, which are then mounted within a mechanical press.

Abstract translation: 一种用于产生用于场致发射显示屏的薄均匀粉末磷光体的系统和方法，其中通过将沉积的磷光体层放置在两个光学平面之间的阳极板中来实现荧光粉层的平坦化，然后将它们安装在机械压力机中。

公开(公告)号：US5508228A

公开(公告)日：1996-04-16

申请号：US195434

申请日：1994-02-14

Applicant: Ernest R. Nolan ,  Diana C. Duane ,  Todd H. Herder ,  Thomas A. Bishop ,  Kimcuc T. Tran ,  Robert W. Froehlich ,  Randy L. German ,  Richard D. Nelson ,  Chung J. Lee ,  Mark R. Breen ,  Kathryn V. Keswick

Inventor： Ernest R. Nolan ,  Diana C. Duane ,  Todd H. Herder ,  Thomas A. Bishop ,  Kimcuc T. Tran ,  Robert W. Froehlich ,  Randy L. German ,  Richard D. Nelson ,  Chung J. Lee ,  Mark R. Breen ,  Kathryn V. Keswick

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  Y10S438/903

Abstract: Compliant electrically connection bumps for an adhesive flip chip integrated circuit device and various methods for forming the bumps include the steps of forming polymer bumps on a substrate or an integrated circuit die and coating the polymer bumps with a metallization layer. The polymer bump forming step includes the steps of coating a polymer material on a substrate, curing the polymer and the etching the bump pattern from the polymer material. The overcoating step includes electrolessly plating a ductile metal such as gold on the polymer bump.

Abstract translation: 用于粘合倒装芯片集成电路器件的合适的电连接凸块和用于形成凸块的各种方法包括以下步骤：在衬底或集成电路裸片上形成聚合物凸块并用金属化层涂覆聚合物凸块。 聚合物凸块形成步骤包括以下步骤：在基材上涂覆聚合物材料，固化聚合物和从聚合物材料蚀刻凸块图案。 外涂步骤包括在聚合物凸块上无电镀电镀金属如金。

公开(公告)号：US5449970A

公开(公告)日：1995-09-12

申请号：US995846

申请日：1992-12-23

Applicant: Nalin Kumar ,  Chenggang Xie

Inventor： Nalin Kumar ,  Chenggang Xie

IPC: G09G3/22 ,  G09G3/30 ,  H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J29/08 ,  H01J29/28 ,  H01J31/12 ,  H01J61/067 ,  H01J63/06 ,  H01J1/30

CPC classification number: H01J1/304 ,  G09G3/22 ,  H01J1/3042 ,  H01J29/085 ,  H01J31/127 ,  H01J61/0677 ,  H01J63/06 ,  H01J9/027 ,  H01J2201/304 ,  H01J2201/30426 ,  H01J2201/30457 ,  H01J2201/319 ,  H01J2329/8625 ,  H01J2329/864

Abstract: A matrix-addressed diode flat panel display of field emission type is described, utilizing a diode (two terminal) pixel structure. The flat panel display includes a cathode assembly having a plurality of cathodes, each cathode including a layer of cathode conductive material and a layer of a low effective work-function material deposited over the cathode conductive material and an anode assembly having a plurality of anodes, each anode including a layer of anode conductive material and a layer of cathodoluminescent material deposited over the anode conductive material, the anode assembly located proximate the cathode assembly to thereby receive charged particle emissions from the cathode assembly, the cathodoluminescent material emitting light in response to the charged particle emissions. The flat panel display further includes the capability for selectively varying field emission between the plurality of corresponding light-emitting anodes and field-emission cathodes to thereby effect an addressable grey-scale operation of the flat panel display.

Abstract translation: 利用二极管（二端）像素结构描述场发射型矩阵寻址二极管平板显示器。 平板显示器包括具有多个阴极的阴极组件，每个阴极包括阴极导电材料层和沉积在阴极导电材料上的低有效功函数材料层和具有多个阳极的阳极组件， 每个阳极包括阳极导电材料层和沉积在阳极导电材料上的阴极发光材料层，阳极组件位于阴极组件附近，从而接收来自阴极组件的带电粒子发射，阴极发光材料响应于 带电粒子排放。 平板显示器还包括用于选择性地改变多个对应的发光阳极和场致发射阴极之间的场发射的能力，从而实现平板显示器的可寻址的灰度级操作。

公开(公告)号：US5383269A

公开(公告)日：1995-01-24

申请号：US114865

申请日：1993-09-02

Applicant: Claude Rathmell ,  Carroll S. Vance ,  David W. Barnes ,  Seyed H. Hashemi

Inventor： Claude Rathmell ,  Carroll S. Vance ,  David W. Barnes ,  Seyed H. Hashemi

IPC: H01L21/98 ,  H01L25/10 ,  H05K3/36

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2225/1058 ,  H01L2924/1627 ,  Y10T29/49126 ,  Y10T29/49172

Abstract: A three dimensional integrated circuit interconnect for connecting a plurality of chips in a module with a standard footprint for pin grid array or quad flat pack mounting. Each IC is mounted on a custom interconnect slice and tested. The slices are stacked together with electrical connections from one slice layer to the next. The module may use multi-layer ceramic slices or printed circuit board materials.

Abstract translation: 一种三维集成电路互连，用于将模块中的多个芯片连接到用于针阵列阵列或四方扁平封装安装的标准封装。 每个IC都安装在定制的互连片上并进行测试。 这些切片与从一个切片层到下一个切片层的电连接堆叠在一起。 该模块可以使用多层陶瓷片或印刷电路板材料。

公开(公告)号：US5382315A

公开(公告)日：1995-01-17

申请号：US120264

申请日：1993-09-13

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01J9/02 ,  H01L21/48 ,  H01L21/60 ,  H01L23/485 ,  H05K1/14 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/14 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/465 ,  H01J9/025 ,  H01L21/4857 ,  H01L24/11 ,  H01L24/13 ,  H05K3/045 ,  H05K3/184 ,  H01J2201/30407 ,  H01J2201/30457 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/19041 ,  H05K1/142 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0376 ,  H05K2201/2081 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/1338 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/143 ,  H05K3/146 ,  H05K3/185 ,  H05K3/388 ,  H05K3/4644 ,  H05K3/4661 ,  Y10S438/942

Abstract: A method of forming an etch mask and patterning a substrate. The method includes directing a particle beam at a substrate without using a mask to deposit an etch mask on the substrate which selectively exposes predetermined portions of the substrate, the etch mask consisting of particles mechanically placed on the substrate by the particle beam, and then etching the exposed portions of the substrate through the etch mask to form channels therein. The process is well suited to fabricating high density copper/polyimide multi-chip modules.

Abstract translation: 一种形成蚀刻掩模和图案化衬底的方法。 该方法包括在基板上引导粒子束而不使用掩模在基板上沉积选择性地暴露基板的预定部分的蚀刻掩模，该蚀刻掩模由颗粒束机械地放置在基板上的颗粒组成，然后蚀刻 通过蚀刻掩模的衬底的暴露部分在其中形成通道。 该工艺非常适合制造高密度铜/聚酰亚胺多芯片模块。