公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20160163555A1

公开(公告)日：2016-06-09

申请号：US14676097

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/823456 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823431

Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

Abstract translation: 本文公开了形成具有不同间距间距和临界尺寸的特征的方法。 一种方法包括在半导体衬底上形成下层材料。 该方法还包括在材料的下层上形成掩模层。 掩模层包括位于衬底的第一区域上方的特征，以及位于衬底的第二区域之上的特征。 这些特征具有不同的间距和关键尺寸。 该方法还包括通过掩模层对材料的下层进行至少一个蚀刻工艺。

公开(公告)号：US20150064912A1

公开(公告)日：2015-03-05

申请号：US14014906

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Linus Jang ,  Young Joon Moon ,  Ryan Ryoung Han Kim

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823456

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法，其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴，其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

公开(公告)号：US10283505B2

公开(公告)日：2019-05-07

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/52 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L23/528 ,  H01L21/02 ,  H01L21/321 ,  H01L27/02 ,  H01L29/49

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US09431264B2

公开(公告)日：2016-08-30

申请号：US14014906

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Linus Jang ,  Young Joon Moon ,  Ryan Ryoung Han Kim

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823456

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法，其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴，其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

公开(公告)号：US20150318181A1

公开(公告)日：2015-11-05

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09449835B2

公开(公告)日：2016-09-20

申请号：US14676097

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/823456 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823431

Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

Abstract translation: 本文公开了形成具有不同间距间距和临界尺寸的特征的方法。 一种方法包括在半导体衬底上形成下层材料。 该方法还包括在材料的下层上形成掩模层。 掩模层包括位于衬底的第一区域上方的特征，以及位于衬底的第二区域之上的特征。 这些特征具有不同的间距和关键尺寸。 该方法还包括通过掩模层对材料的下层进行至少一个蚀刻工艺。

公开(公告)号：US09184263B2

公开(公告)日：2015-11-10

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。

公开(公告)号：US20150255299A1

公开(公告)日：2015-09-10

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。