公开(公告)号：US20200291538A1

公开(公告)日：2020-09-17

申请号：US16351116

申请日：2019-03-12

Applicant: Infineon Technologies AG

Inventor： Norbert Pielmeier ,  Chin Yung Lai ,  Swee Kah Lee ,  Muhammad Muhammat Sanusi ,  Evelyn Napetschnig ,  Nurfarena Othman ,  Siew Ching Seah

IPC: C25D7/12 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  C25D3/38

Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 μm to 10 μm. A method of manufacturing a metal surface with such micropores also is described.

公开(公告)号：US20200043876A1

公开(公告)日：2020-02-06

申请号：US16520597

申请日：2019-07-24

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Wei Cheat Lee ,  Wei Lee Lim ,  Frank Renner ,  Michael Rogalli

IPC: H01L23/00

Abstract: A package includes an electronic chip having a pad. The pad is at least partially covered with adhesion enhancing structures. The pad and the adhesion enhancing structures have at least aluminium in common.

公开(公告)号：US10276362B2

公开(公告)日：2019-04-30

申请号：US15141855

申请日：2016-04-29

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Sandra Wirtitsch ,  Mario Barusic ,  Aleksander Hinz ,  Robert Hartl ,  Georg Schinner

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/167

Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.

公开(公告)号：US20180082848A1

公开(公告)日：2018-03-22

申请号：US15692495

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L21/285 ,  H01L23/00 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US09484316B2

公开(公告)日：2016-11-01

申请号：US14070334

申请日：2013-11-01

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。

公开(公告)号：US12183696B2

公开(公告)日：2024-12-31

申请号：US18235585

申请日：2023-08-18

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US12040288B2

公开(公告)日：2024-07-16

申请号：US18236858

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Harry Walter Sax ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Evelyn Napetschnig ,  Michael Rogalli

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L21/56 ,  H01L23/3142 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0382 ,  H01L2224/05687 ,  H01L2924/365

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

公开(公告)号：US11776927B2

公开(公告)日：2023-10-03

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

CPC classification number: H01L24/29 ,  B23K35/262 ,  C22C13/02 ,  H01L24/83 ,  H01L2224/2922 ,  H01L2224/29211 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/29264 ,  H01L2224/29269 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US11764176B2

公开(公告)日：2023-09-19

申请号：US17400303

申请日：2021-08-12

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/485 ,  H01L23/53219 ,  H01L23/53233

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US11410950B2

公开(公告)日：2022-08-09

申请号：US17023538

申请日：2020-09-17

Applicant: Infineon Technologies AG

Inventor： Gert Pfahl ,  Daniel Bolowski ,  Marian Sebastian Broll ,  Michael Kreuz ,  Evelyn Napetschnig ,  Holger Schulze ,  Stefan Woehlert

IPC: H01L23/00 ,  C22C21/10 ,  C22C21/16 ,  C22C21/02

Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.