中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.066 seconds)

    Wireline receiver circuitry having collaborative timing recovery
    21.
    发明授权
    Wireline receiver circuitry having collaborative timing recovery 有权
    有线接收器电路具有协作定时恢复

    公开(公告)号：US09374250B1

    公开(公告)日：2016-06-21

    申请号：US14573343

    申请日：2014-12-17

    Applicant: Intel Corporation

    Inventor： Tawfiq Musah ,  Gokce Keskin ,  Ganesh Balamurugan ,  James E. Jaussi ,  Bryan K. Casper

    IPC: H03H7/30 ,  H04L25/03 ,  H04L7/02

    CPC classification number: H04L25/03057 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03146 ,  H04L25/14

    Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

    Abstract translation: 一些实施例包括具有用于接收输入信号的输入的装置和方法，用于接收具有不同相位以对输入信号进行采样的时钟信号的附加输入以及具有DFE切片的判决反馈均衡器（DFE）。 DFE片包括多个数据比较器，用于基于输入信号的采样来提供数据信息，以及多个相位误差比较器，以提供与输入信号的采样相关联的相位误差信息。 DFE切片的相位误差比较器的数量不大于DFE切片的数据比较器的数量。

    Systems, methods, and apparatuses for stacked memory
    22.
    发明授权
    Systems, methods, and apparatuses for stacked memory 有权

    公开(公告)号：US10956268B2

    公开(公告)日：2021-03-23

    申请号：US16529716

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/12 ,  G11C5/02

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Patent Agency Ranking