公开(公告)号：US09466692B2

公开(公告)日：2016-10-11

申请号：US14699746

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract translation: 一种制造用于半导体器件的替代栅极堆叠的方法包括在去除伪栅极之后的以下步骤：在由虚拟栅极空出的区域上生长高k电介质层; 在高k电介质层上沉积薄金属层; 在所述薄金属层上沉积牺牲层; 执行第一快速热退火; 去除牺牲层; 以及沉积用于间隙填充的低电阻率金属的金属层。

公开(公告)号：US20160043088A1

公开(公告)日：2016-02-11

申请号：US14452762

申请日：2014-08-06

Applicant: International Business Machines Corporation

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

Abstract translation: 可以使用沟槽电容器形成具有可编程泄漏的非易失性存储器件。 在形成深沟槽之后，使用介电材料在深沟槽的表面上形成金属 - 绝缘体 - 金属堆叠，该电介质材料在施加编程偏置电压时产生泄漏路径细丝。 可以形成一组编程晶体管和漏电读出装置来编程和读取泄漏电平的状态。 非易失性存储器件可以通过形成多个深沟槽，沉积外部金属层和节点电介质层的堆叠而形成动态随机存取存储器（DRAM）器件，同时形成图案化该节点电介质层 为每个非易失性存储器件提供第一节点电介质，其比每个DRAM器件的第二节点电介质薄，并且形成内部金属层。

公开(公告)号：US20150243761A1

公开(公告)日：2015-08-27

申请号：US14699746

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US08932949B2

公开(公告)日：2015-01-13

申请号：US14258063

申请日：2014-04-22

Applicant: International Business Machines Corporation

Inventor： Eduard A. Cartier ,  Brian J. Greene ,  Dechao Guo ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/785 ,  H01L21/02323 ,  H01L21/28017 ,  H01L27/1211 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

公开(公告)号：US10978551B2

公开(公告)日：2021-04-13

申请号：US15832250

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Vijay Narayanan

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/02 ,  H01L21/285 ,  H01L23/48

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

公开(公告)号：US20180277623A1

公开(公告)日：2018-09-27

申请号：US15469860

申请日：2017-03-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Vijay Narayanan

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28568 ,  H01L23/481 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/90

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

公开(公告)号：US20180122491A1

公开(公告)日：2018-05-03

申请号：US15337594

申请日：2016-10-28

Applicant: International Business Machines Corporation

Inventor： Eduard A. Cartier ,  Chandrasekharan Kothandaraman

IPC: G11C17/16 ,  H01L29/51 ,  H01L27/112 ,  G11C17/18 ,  H01L29/78 ,  H01L23/525

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L23/5256 ,  H01L27/11206 ,  H01L29/517 ,  H01L29/78

Abstract: A fuse structure includes a substrate, a gate dielectric formed on the substrate, a gate electrode formed on the gate dielectric, and first and second source/drain regions formed on the substrate on opposite sides with respect to the gate electrode, wherein the gate dielectric is configured such that a plurality of oxygen vacancies trapping respective charges are formed upon application of a pulse to the gate electrode.

公开(公告)号：US09911597B2

公开(公告)日：2018-03-06

申请号：US15595503

申请日：2017-05-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/322 ,  H01L21/20 ,  H01G4/005 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US20170358588A1

公开(公告)日：2017-12-14

申请号：US15647590

申请日：2017-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Chandrasekharan Kothandaraman

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L21/31155 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/11568 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66833 ,  H01L29/792

Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.

公开(公告)号：US09634116B2

公开(公告)日：2017-04-25

申请号：US15058512

申请日：2016-03-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Barry P. Linder ,  Vijay Narayanan

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/28 ,  H01L21/30 ,  H01L29/49 ,  H01L21/285 ,  H01L21/306 ,  H01L21/324 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/3003 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.