公开(公告)号：US20230187477A1

公开(公告)日：2023-06-15

申请号：US17548546

申请日：2021-12-12

Applicant: Intel Corporation

Inventor： Martin Ostermayr ,  Georg Seidemann ,  Walther Lutz ,  Joachim Assenmacher

IPC: H01L49/02 ,  H01L29/732

CPC classification number: H01L28/60 ,  H01L29/732

Abstract: Capacitors based on stacks of nanoribbons and associated devices and systems are disclosed. In particular, a stack of at least two nanoribbons may be used to provide a two-terminal device referred to herein as a “nanoribbon-based capacitor,” where one nanoribbon serves as a first capacitor electrode and another nanoribbon serves as a second capacitor electrode. Using portions of nanoribbon stacks to implement nanoribbon-based capacitors could provide an appealing alternative to conventional capacitor implementations because it would require only modest process changes compared to fabrication of nanoribbon-based FETs and because nanoribbon-based capacitors could be placed close to active devices. Furthermore, with a few additional process steps, nanoribbon-based capacitors may, advantageously, be extended to implement other circuit blocks such as nanoribbon-based BJTs or three-nanoribbon arrangements with a common connection between two anodes and a separate connection to a cathode.

公开(公告)号：US20230163170A1

公开(公告)日：2023-05-25

申请号：US17530836

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Martin Ostermayr ,  Joachim Assenmacher ,  Georg Seidemann ,  Klaus Herold ,  Walther Lutz

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66742

Abstract: Fabrication methods that may provide greater versatility in tuning threshold voltage of transistors implemented in different nanoribbons within a given stack and in tuning threshold voltage of transistors implemented in adjacent nanoribbon stacks, as well as corresponding devices, are disclosed. An example fabrication method includes selectively doping portions of semiconductor layers from which individual nanoribbons will be formed later. The selective doping is performed on a layer-by-layer basis, i.e., after a given semiconductor layer is deposited and before the next layer is deposited. In this manner, some nanoribbons of a given nanoribbon stack may be doped, while other nanoribbons of the same stack may be substantially undoped, or, more generally, different nanoribbons of a given nanoribbon stack may have different dopant concentrations. The differences in the dopant concentration of different nanoribbons within the stack advantageously allows forming transistors with different threshold voltages in a single nanoribbon stack.

公开(公告)号：US20220415806A1

公开(公告)日：2022-12-29

申请号：US17355747

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/50

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

公开(公告)号：US20220415805A1

公开(公告)日：2022-12-29

申请号：US17355726

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/50 ,  H01L23/522 ,  H01L23/36

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

公开(公告)号：US10319688B2

公开(公告)日：2019-06-11

申请号：US14361625

申请日：2013-12-09

Applicant: INTEL CORPORATION

Inventor： Andreas Wolter ,  Saravana Maruthamuthu ,  Mikael Knudsen ,  Thorsten Meyer ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01Q1/38 ,  H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01Q1/50 ,  H01Q1/52 ,  H01L23/29

Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.

公开(公告)号：US09921694B2

公开(公告)日：2018-03-20

申请号：US14778142

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Teodora Ossiander ,  Andreas Wolter ,  Sonja Koller ,  Georg Seidemann ,  Jan Proschwitz ,  Hans-Joachim Barth ,  Bastiaan Elshof

IPC: G09G5/00 ,  G06F3/044 ,  H04B1/3827 ,  G01L1/24 ,  G06F1/16 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F3/0354

CPC classification number: G06F3/044 ,  G01L1/24 ,  G06F1/163 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F2203/04102 ,  G06F2203/04109 ,  H04B1/385

Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.

公开(公告)号：US20160240492A1

公开(公告)日：2016-08-18

申请号：US14361625

申请日：2013-12-09

Applicant: INTEL CORPORATION

Inventor： Andreas Wolter ,  Saravana Maruthamuthu ,  Mikael Knudsen ,  Meyer Thorsten ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01L23/66 ,  H01Q1/50 ,  H01Q1/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01Q1/38 ,  H01L23/48

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01Q1/38 ,  H01Q1/50 ,  H01Q1/526 ,  H01L2924/00

Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.

Abstract translation: 在可用于封装模具的陶瓷上描述天线。 在一个示例中，封装具有管芯，管芯上的陶瓷衬底，附着到陶瓷衬底的天线以及将天线电连接到管芯的导电引线。

公开(公告)号：US09142475B2

公开(公告)日：2015-09-22

申请号：US13965746

申请日：2013-08-13

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L23/32 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有磁性触点的集成电路（IC）封装组件，以及包含这种磁性触点的对应的制造方法和系统。 第一IC基板可以具有与第一电路径特征耦合的第一磁体。 第二IC基板可以具有与第二电路径特征耦合的第二磁体。 磁体可以嵌入在IC基板和/或电路径特征中。 磁体可以产生延伸穿过第一和第二电路由特征之间的间隙的磁场。 可以将导电磁性颗粒施加到IC基板中的一个或两个以形成跨越间隙延伸的磁互连结构。 在一些实施例中，通过将磁体加热到对应的部分退磁温度（PDT）或居里温度，磁接触件可以去磁。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20250157941A1

公开(公告)日：2025-05-15

申请号：US19025226

申请日：2025-01-16

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：US12191571B2

公开(公告)日：2025-01-07

申请号：US17323278

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/48 ,  H01Q15/08

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.