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    Contact structure of semiconductor devices and method of fabricating the same
    21.
    发明授权
    Contact structure of semiconductor devices and method of fabricating the same 有权
    半导体器件的接触结构及其制造方法

    公开(公告)号：US07180188B2

    公开(公告)日：2007-02-20

    申请号：US10833548

    申请日：2004-04-28

    申请人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

    发明人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814

    摘要： A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

    摘要翻译： 接触结构包括设置在半导体衬底的预定区域上的下导电图案。 下导电层在其顶表面的预定区域具有凹区。 嵌入导电层填充凹区域。 嵌入导电层的顶表面至少与下导电图案的平坦顶表面的高度一样高。 模具层设置成覆盖半导体衬底，下导电图案和嵌入导电层。 上部导电图案以凹版图案布置。 凹版图案设置在模具层中以暴露嵌入导电层的预定区域。

    Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches
    28.
    发明授权
    Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches 有权
    使用图案密度和沟槽深度的参数制造半导体器件的方法包括平坦化导电层

    公开(公告)号：US07737038B2

    公开(公告)日：2010-06-15

    申请号：US11567927

    申请日：2006-12-07

    申请人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

    发明人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3212 ,  B24B37/013 ,  B24B49/105 ,  H01L22/26 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上在具有多个沟槽的绝缘层上形成导电层，使得导电层填充在绝缘层中形成的多个沟槽中，并计算目标涡流值 使用模式密度和沟槽深度的参数来测量终点。 该方法还包括使用涡流监测系统平坦化导电层并测量导电层上的涡流值，并且当测量的涡流值达到目标涡流值时停止平坦化，以形成具有目标高度的平坦化导电层 在绝缘层上。

    Methods of fabricating semiconductor device using sacrificial layer
    29.
    发明授权
    Methods of fabricating semiconductor device using sacrificial layer 有权
    使用牺牲层制造半导体器件的方法

    公开(公告)号：US07348277B2

    公开(公告)日：2008-03-25

    申请号：US11352640

    申请日：2006-02-13

    申请人： Ja-Eung Koo ,  Byung-Lyul Park

    发明人： Ja-Eung Koo ,  Byung-Lyul Park

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7688 ,  H01L21/76819

    摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

    摘要翻译： 提供了使用牺牲层制造半导体器件的方法。 这些方法提供了一种在大理石工艺中进行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。 为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。 在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。 在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。 依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。 在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

    Method of Fabricating Semiconductor Device Including Planarizing Conductive Layer Using Parameters of Pattern Density and Depth of Trenches
    30.
    发明申请
    Method of Fabricating Semiconductor Device Including Planarizing Conductive Layer Using Parameters of Pattern Density and Depth of Trenches 有权
    使用图案密度和沟槽深度的参数制造包括平面化导电层的半导体器件的方法

    公开(公告)号：US20070196994A1

    公开(公告)日：2007-08-23

    申请号：US11567927

    申请日：2006-12-07

    申请人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

    发明人： Seung-Mahn Lee ,  Byung-Lyul Park ,  MooJin Jung

    IPC分类号： H01L21/20

    CPC分类号： H01L21/3212 ,  B24B37/013 ,  B24B49/105 ,  H01L22/26 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上在具有多个沟槽的绝缘层上形成导电层，使得导电层填充在绝缘层中形成的多个沟槽中，并计算目标涡流值 使用模式密度和沟槽深度的参数来测量终点。 该方法还包括使用涡流监测系统平坦化导电层并测量导电层上的涡流值，并且当测量的涡流值达到目标涡流值时停止平坦化，以形成具有目标高度的平坦化导电层 在绝缘层上。