公开(公告)号：US06924176B2

公开(公告)日：2005-08-02

申请号：US10103696

申请日：2002-03-25

申请人： Toru Yoshie ,  Kazuhide Abe ,  Yusuke Harada

发明人： Toru Yoshie ,  Kazuhide Abe ,  Yusuke Harada

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/525 ,  H01L21/82 ,  H01L21/26 ,  H01L21/326

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.

摘要翻译： 形成在半导体衬底上的绝缘层上的导电层通过穿过绝缘层并到达半导体衬底的贯穿部连接到半导体衬底。 在导电层通过贯通部分电连接到半导体衬底的状态下，在导电层上进行使用等离子体蚀刻的图案化工艺，从而形成导电路径。 在形成导电路径之后，在衬底或导电路径上进行加热处理，以便通过与其接触的通孔部分和半导体衬底之间的反应而断开通孔部分和衬底之间的电连接 。

公开(公告)号：US20050151224A1

公开(公告)日：2005-07-14

申请号：US10910318

申请日：2004-08-04

申请人： Kazuhide Abe

发明人： Kazuhide Abe

IPC分类号： H01L21/288 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/532 ,  H01L29/00

CPC分类号： H01L23/5226 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

摘要翻译： 半导体器件具有半导体衬底，形成在半导体衬底的表面上的第一绝缘膜，形成在第一绝缘膜中的第一凹槽，形成在除了顶部周边区域之外的第一绝缘膜的内表面上的第一阻挡膜 形成在第一沟槽中的第一导电膜和形成在第一导电膜的上表面和顶周边区域上的覆盖膜和第一阻挡膜的上表面。 第一导电膜包括铜。

公开(公告)号：US20050087872A1

公开(公告)日：2005-04-28

申请号：US10766739

申请日：2004-01-29

申请人： Kazuhide Abe

发明人： Kazuhide Abe

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The wiring structure of a semiconductor device of the invention enhances the dielectric strength of the wirings and reduces the capacitance across the wirings, by preventing a diffusion of the wiring material. The wiring structure includes a first insulating film, plural wiring films, plural barrier films, and plural cap films. The first insulating film has plural grooves formed thereon, and has an interface in the horizontal direction between the adjoining grooves. The wiring films are formed to protrude from the interface each by the grooves of the first insulating film. The barrier films are formed on the bottoms of the wiring films, and also on side faces of the wiring films to a height exceeding the interface. The cap films are formed at least on the upper faces of the wiring films, and are separated each by the grooves.

摘要翻译： 本发明的半导体器件的布线结构通过防止布线材料的扩散，增强布线的介电强度并降低布线两端的电容。 布线结构包括第一绝缘膜，多个布线膜，多个阻挡膜和多个盖膜。 第一绝缘膜具有形成在其上的多个槽，并且在相邻的槽之间具有在水平方向上的界面。 布线膜形成为从第一绝缘膜的沟槽各自的界面突出。 阻挡膜形成在布线膜的底部以及布线膜的侧面上，达到超过界面的高度。 盖膜至少形成在布线膜的上表面上，并由沟槽分开。

公开(公告)号：US06870446B2

公开(公告)日：2005-03-22

申请号：US10252105

申请日：2002-09-23

申请人： Ryoichi Ohara ,  Kazuhide Abe ,  Takashi Kawakubo ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Ryuichi Fujimoto

发明人： Ryoichi Ohara ,  Kazuhide Abe ,  Takashi Kawakubo ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Ryuichi Fujimoto

IPC分类号： H03H9/00 ,  H03H9/54 ,  H03H9/58 ,  H03H9/60

CPC分类号： H03H9/605 ,  H03H9/0095 ,  H03H9/542 ,  H03H9/581 ,  H03H2009/02196

摘要： A high frequency filter comprises thin film piezoelectric resonators connected in series between the input/output nodes, thin film piezoelectric resonators connected in parallel between the input/output nodes and a variable voltage circuit adapted to change the voltage applied to at least either the thin film piezoelectric resonators connected in series or the thin film piezoelectric resonators connected in parallel. The resonance characteristic of at least either the thin film piezoelectric resonators connected in series or the thin film piezoelectric resonator connected in parallel is shifted by changing the voltage applied by the variable voltage circuit to change the pass characteristic of the filter.

摘要翻译： 高频滤波器包括串联连接在输入/输出节点之间的薄膜压电谐振器，并联连接在输入/输出节点之间的薄膜压电谐振器和可变电压电路，可变电压电路适于改变施加到至少薄膜的电压 串联连接的压电谐振器或并联连接的薄膜压电谐振器。 串联连接的薄膜压电谐振器或并联连接的薄膜压电谐振器中的至少一个的谐振特性通过改变由可变电压电路施加的电压来改变滤波器的通过特性而被移位。

公开(公告)号：US06809604B2

公开(公告)日：2004-10-26

申请号：US10397876

申请日：2003-03-27

申请人： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Ryuichi Fujimoto

发明人： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Ryuichi Fujimoto

IPC分类号： H03B532

CPC分类号： H03H9/173 ,  H03H9/0095 ,  H03H9/545 ,  H03H9/562 ,  H03H9/564 ,  H03H9/566 ,  H03H9/581 ,  H03H9/585 ,  H03H9/60 ,  H03H2009/02196

摘要： To provide a miniaturized voltage controlled oscillator which can oscillate simultaneously a plurality of frequencies and has high stability of frequency, an excellent low phase noise, small variation per hour, and a wide frequency variable range. A thin film bulk acoustic wave resonator using single crystal ferroelectric material equal to or smaller than 10 &mgr;m in thickness whose direction of polarization is aligned to the direction of thickness is utilized as the piezoelectric member. The voltage controlled oscillator having large changing rate of the oscillation frequency of 0.01%/V or more and an extremely small phase noise is provided by changing the voltage applied to the electrodes.

摘要翻译： 为了提供能够同时振荡多个频率并且具有高的频率稳定性，优异的低相位噪声，小时变化小和宽频率可变范围的微型压控振荡器.1。一种使用单晶的薄膜体声波谐振器 作为压电部件，利用等于或小于10μm厚的偏振方向与厚度方向对准的铁电材料。 通过改变施加到电极上的电压，提供振荡频率变化率大于0.01％/ V以上且极小相位噪声的压控振荡器。

公开(公告)号：US06767812B2

公开(公告)日：2004-07-27

申请号：US09984383

申请日：2001-10-30

申请人： Kazuhide Abe ,  Yusuke Harada

发明人： Kazuhide Abe ,  Yusuke Harada

IPC分类号： H01L2128

CPC分类号： C23C16/0272 ,  C23C16/14

摘要： Before deposition of a CVD titanium film on a cobalt silicide layer, an element which reacts with titanium is provided in the cobalt silicide layer in advance. Thereafter, the CVD titanium film is deposited on the cobalt silicide using a titanium tetrachloride gas.

摘要翻译： 在将CVD钛膜沉积在硅化钴层上之前，预先在钴硅化物层中提供与钛反应的元素。 此后，使用四氯化钛气体将CVD钛膜沉积在硅化钴上。

公开(公告)号：US5889696A

公开(公告)日：1999-03-30

申请号：US45958

申请日：1998-03-23

申请人： Takashi Kawakubo ,  Noburu Fukushima ,  Kazuhide Abe

发明人： Takashi Kawakubo ,  Noburu Fukushima ,  Kazuhide Abe

IPC分类号： H01L27/10 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C11/22

摘要： A semiconductor memory device is constituted by arranging a plurality of memory cells in a matrix format, each of which includes a thin-film capacitor having a ferroelectric film and a pair of electrodes facing each other via the ferroelectric film, and a transfer gate transistor connected to the thin film capacitor. A voltage corresponding to the width of a hysteresis curve obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 20% or lower of the voltage difference between the positive and negative directions in a writing operation. A remanent polarization amount obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 30% or lower of the total polarization amount obtained upon application of a voltage in the writing operation.

摘要翻译： 半导体存储器件通过以矩阵形式布置多个存储单元而构成，每个存储单元包括具有铁电膜的薄膜电容器和经由铁电体膜相互面对的一对电极，并且连接有传输栅极晶体管 到薄膜电容器。 当薄膜电容器饱和和极化时获得的滞后曲线的宽度对应的电压落在写入操作中正负方向之间的电压差的5％以上至20％以下的范围内。 当薄膜电容器饱和和极化时获得的剩余极化量落在在写入操作中施加电压时获得的总极化量的5％以上至30％以下的范围内。

公开(公告)号：US09041182B2

公开(公告)日：2015-05-26

申请号：US13688823

申请日：2012-11-29

申请人： Toshihiko Nagano ,  Kazuhide Abe ,  Hiroshi Yamada ,  Kazuhiko Itaya ,  Taihei Nakada

发明人： Toshihiko Nagano ,  Kazuhide Abe ,  Hiroshi Yamada ,  Kazuhiko Itaya ,  Taihei Nakada

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/00 ,  H01L23/66

CPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14181 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2224/81 ,  H01L2924/01079 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

摘要翻译： 根据实施例的半导体封装包括：半导体芯片，其前表面包括前电极，背面具有背电极; 在半导体芯片和前侧盖部分之间的部分中包括气隙的前侧盖部分和前侧穿透电极，并且被定位成面向半导体芯片的前表面; 与第一帽部接合以密封半导体芯片的背面盖部分至少在半导体芯片和背面侧帽部分之间的部分和背面贯通电极之间包括气隙，并且位于 面对半导体芯片的背面; 电连接前电极和前侧穿透电极的前侧连接部; 以及将背面电极和背面贯通电极电连接的背面侧连接部。

公开(公告)号：US08419497B2

公开(公告)日：2013-04-16

申请号：US12923949

申请日：2010-10-15

申请人： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

发明人： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

IPC分类号： H01J9/00

CPC分类号： H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

摘要翻译： 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US20120228755A1

公开(公告)日：2012-09-13

申请号：US13235386

申请日：2011-09-18

申请人： Toshihiko NAGANO ,  Hiroshi Yamada ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Taihei Nakada

发明人： Toshihiko NAGANO ,  Hiroshi Yamada ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Taihei Nakada

IPC分类号： H01L23/053 ,  H01L21/56

CPC分类号： H01L23/04 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00

摘要： A semiconductor module includes a high frequency chip, an insulating cap, a through electrode, interconnections, and an insulating layer. The insulating cap forms a hollow with the chip to cover the chip. The through electrode passes through a first plane of the cap and a second plane of the cap, the first plane facing the chip, the second plane being on a side opposite to the first plane. The interconnections are provided on the cap and connected to the through electrode. The insulating layer is provided on the cap and fills a portion between the interconnections therewith.

摘要翻译： 半导体模块包括高频芯片，绝缘帽，通孔，互连和绝缘层。 绝缘盖形成具有芯片的中空以覆盖芯片。 所述贯通电极通过所述盖的第一平面和所述盖的第二平面，所述第一平面面向所述芯片，所述第二平面位于与所述第一平面相对的一侧。 互连设置在盖上并连接到通孔。 绝缘层设置在盖上并填充与其互连之间的部分。