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    LOW-TEMPERATURE METHODS FOR SPONTANEOUS MATERIAL SPALLING
    27.
    发明申请
    LOW-TEMPERATURE METHODS FOR SPONTANEOUS MATERIAL SPALLING 审中-公开
    用于自发材料膨胀的低温方法

    公开(公告)号：US20120309269A1

    公开(公告)日：2012-12-06

    申请号：US13150813

    申请日：2011-06-01

    申请人： Maha M. Khayyat ,  Norma E. Sosa Cortes ,  Katherine L. Saenger ,  Stephen W. Bedell ,  Devendra K. Sadana

    发明人： Maha M. Khayyat ,  Norma E. Sosa Cortes ,  Katherine L. Saenger ,  Stephen W. Bedell ,  Devendra K. Sadana

    IPC分类号： B24B1/00

    CPC分类号： H01L21/187

    摘要： Method to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths are provided. In one embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature. Next, the base substrate including the stressor layer is brought to a second temperature which is less than room temperature. The base substrate is spalled at the second temperature to form a spalled material layer. Thereafter, the spalled material layer is returned to room temperature, i.e., the first temperature.

    摘要翻译： 方法：（i）对材料剥落过程引入额外的控制，从而改善裂纹的产生和传播，并提供（ii）提高选择性剥落深度的范围。 在一个实施例中，该方法包括在室温下的第一温度下在基底基板的表面上提供应力层。 接下来，包括应力层的基底衬底达到小于室温的第二温度。 基底基板在第二温度下剥离以形成剥离的材料层。 此后，剥离的材料层返回到室温，即第一温度。

    CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
    29.
    发明授权
    CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 有权
    具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片

    公开(公告)号：US08241970B2

    公开(公告)日：2012-08-14

    申请号：US12197459

    申请日：2008-08-25

    申请人： Guy M. Cohen ,  Katherine L. Saenger

    发明人： Guy M. Cohen ,  Katherine L. Saenger

    IPC分类号： H01L21/00

    CPC分类号： H01L27/0924 ,  H01L21/34 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

    摘要： An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different from each other. A volume of material is formed that extends through the first layer from the second layer up to the surface of the first layer. The material has a crystalline orientation that substantially matches the orientation of the second layer. Areas of the surface of the first layer that are outside of the region are selectively etched to create a first plurality of fins and areas inside the region to create a second plurality of fins. The etching leaves the first and second pluralities of fins parallel to each other with different surface crystal orientations.

    摘要翻译： 制造具有至少一个p-FinFET器件和至少一个彼此平行的n-FinFET器件的集成电路。 具有第一晶体取向的第一硅层被结合到具有第二晶体取向的第二硅层上。 第一和第二取向彼此不同。 形成一定体积的材料，其从第二层延伸穿过第一层直到第一层的表面。 该材料具有基本上与第二层的取向一致的晶体取向。 选择性地蚀刻在区域外部的第一层的表面的区域，以在该区域内产生第一多个散热片和区域，以产生第二多个散热片。 蚀刻使得第一和第二多个翅片彼此平行但具有不同的表面晶体取向。