公开(公告)号：US09502490B2

公开(公告)日：2016-11-22

申请号：US14283980

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L49/02 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46 ,  H01L23/50

CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

公开(公告)号：US20160327590A1

公开(公告)日：2016-11-10

申请号：US14703677

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: G01R1/073 ,  G01R29/08 ,  G01R31/28

CPC classification number: G01R1/045 ,  G01R1/06722 ,  G01R1/06772 ,  G01R1/07314 ,  G01R29/08 ,  G01R31/2822

Abstract: Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

Abstract translation: 本公开内容的实施例提供了一种用于测试电子设备的方法和装置。 电子设备安装在测试插座导轨中。 推动器尖端对被引导的同轴弹簧探针施加负载，并强制与设备上的焊盘接触。 测试和接地信号通过设备和测试插座进行路由。 该装置包括具有至少一个被引导的同轴弹簧探针销的插座。 插座引导垫片位于电子设备的插座和插座之间。 插座导轨辅助定位。 推动器尖端放置在与所引导的同轴弹簧探针的相对侧的一侧。 推杆与推动垫片和推杆弹簧配合。 然后将顶部放置在组件上并且用于压缩推动器弹簧并且将引导的同轴弹簧探针针与装置上的垫接合。

公开(公告)号：US09449762B2

公开(公告)日：2016-09-20

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H05K1/03 ,  H01G4/236 ,  H01G2/02 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H05K3/46 ,  H01G2/10 ,  H05K1/02

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20160247761A1

公开(公告)日：2016-08-25

申请号：US14631391

申请日：2015-02-25

Applicant: QUALCOMM INCORPORATED

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/063 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Abstract translation: 集成器件封装包括封装衬底，耦合到封装衬底的管芯，封装管芯的封装层以及配置成作为电感器工作的至少一片导电材料。 导电材料片材至少部分地被封装层封装。 导电材料片被配置为作为螺线管电感器工作。 导电材料片包括第一片部分，第二片部分，其耦合到第一片部分，第一片部分和第二片部分形成电感器的第一绕组，第一端部分耦合到第一片 部分，以及耦合到第二片部分的第二端子部分。 第一片部分形成在片材的第一层上。 第二片部分形成在片材的第二层上。

公开(公告)号：US20160225748A1

公开(公告)日：2016-08-04

申请号：US14609079

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Kyu-Pyung Hwang

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A method for forming a package-on-package (POP) structure is disclosed. The method includes placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package. The post is placed at a distance from a die along a particular axis of the die. The particular axis is substantially parallel to the second surface. The first IC package includes the die. The method also includes forming a conductive path between a second IC package and the first IC package via the post and a solder bump. The solder bump is disposed between the post and the second IC package.

Abstract translation: 公开了一种用于形成封装封装（POP）结构的方法。 该方法包括将柱放置在第一集成电路（IC）封装上，使得布置在柱的第一表面上的焊料涂层位于第一IC封装的柱和第二表面之间。 柱沿模具的特定轴线放置在离模具一定距离处。 特定轴线基本上平行于第二表面。 第一个IC封装包括裸片。 该方法还包括在第二IC封装和第一IC封装之间经由柱和焊料凸块形成导电路径。 焊料凸块设置在柱和第二IC封装之间。

公开(公告)号：US20160142156A1

公开(公告)日：2016-05-19

申请号：US14546924

申请日：2014-11-18

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang

IPC: H04B10/80 ,  H04B10/114

CPC classification number: H04B10/803 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B10/1143 ,  H01L2924/00

Abstract: Some novel features pertain to a device that includes a first integrated device package and a second integrated device package. The first integrated device package includes a first package substrate, a first integrated device, and a first configurable optical transmitter. The first configurable optical transmitter is configured to be in communication with the first integrated device. The first configurable optical transmitter is configured to transmit an optical beam at a configurable angle. The first configurable optical transmitter includes an optical beam source, an optical beam splitter, and a set of phase shifters coupled to the optical beam splitter. The set of phase shifters is configured to enable the angle at which the optical beam is transmitted. The second integrated device package includes a second package substrate, a second integrated device, and a first optical receiver configured to receive the optical beam from the first configurable optical transmitter.

Abstract translation: 一些新颖的特征涉及包括第一集成器件封装和第二集成器件封装的器件。 第一集成器件封装包括第一封装衬底，第一集成器件和第一可配置光发射器。 第一可配置光发射机被配置为与第一集成设备通信。 第一可配置光发射器被配置为以可配置的角度发送光束。 第一可配置光发射机包括光束源，光束分离器和耦合到光束分离器的一组移相器。 该组移相器被配置为使能够发射光束的角度。 第二集成器件封装包括第二封装衬底，第二集成器件和被配置为从第一可配置光发射器接收光束的第一光接收器。

公开(公告)号：US20160141234A1

公开(公告)日：2016-05-19

申请号：US14543560

申请日：2014-11-17

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/498

CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可照像图像层，至少部分地嵌入在可照光成像层中的桥以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。

公开(公告)号：US20160056226A1

公开(公告)日：2016-02-25

申请号：US14468035

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L23/5225 ,  H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal.

Abstract translation: 一些新颖的特征涉及一种集成器件，其包括衬底，多个下层金属层，几个下层电介质层和再分配部分。 再分配部分包括包括第一电介质厚度的第一电介质层和包括第一再分布互连的电磁（EM）无源器件。 第一再分配互连包括第一再分布厚度，其中第一介电厚度比第一再分布厚度大至少约2倍。 在一些实现中，再分配部分包括射频（RF）屏蔽。 在一些实施方案中，RF屏蔽位于钝化层和多个较低级别的介电层之间。 RF屏蔽位于EM无源器件和几个较低级别的介电层之间。 RF屏蔽电耦合到被配置为提供用于接地信号的电路径的互连。

公开(公告)号：US20160055976A1

公开(公告)日：2016-02-25

申请号：US14468212

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: H01G4/30 ,  H01L21/768 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L23/522 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L21/76802 ,  H01L21/7687 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated devices include a substrate, and a capacitor embedded within the substrate. The capacitor is configured to include a first electrode disposed on a first surface, a second electrode disposed on an opposing second surface, and a plurality of capacitor plates extending transverse between the first electrode and the second electrode. Each capacitor plate is electrically coupled to one of the first electrode or the second electrode. A plurality of vias are positioned to extend through the substrate to one of the first electrode or the second electrode. Other aspects, embodiments, and features are also included.

Abstract translation: 集成器件包括衬底和嵌入衬底内的电容器。 电容器被配置为包括设置在第一表面上的第一电极，设置在相对的第二表面上的第二电极和在第一电极和第二电极之间横向延伸的多个电容器板。 每个电容器板电耦合到第一电极或第二电极之一。 定位多个通孔以将基板延伸到第一电极或第二电极之一。 还包括其他方面，实施例和特征。

公开(公告)号：US20140266508A1

公开(公告)日：2014-09-18

申请号：US13835211

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: H03H7/01 ,  H03H3/00 ,  H01G4/40

CPC classification number: H03H7/0115 ,  H01G4/40 ,  H03H3/00 ,  H03H7/12 ,  H05K1/162 ,  H05K2201/09236 ,  Y10T29/43 ,  Y10T29/49016

Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.

Abstract translation: 平面电容器部分地包括围绕其端点之一形成螺旋形环的第一金属线和在第一金属线的环之间形成螺旋形环的第二金属线。 第一和第二金属线是共面的，形成在绝缘层上，并形成平面电容器的第一和第二板。 平面电容器可以用于形成滤波器。 这种过滤器包括形成第一螺旋形环的第一金属线，形成第二螺旋状环的第二金属线和与第一和第二金属线形成环之间的第一和第二金属线形成环的第三金属线 - 共面， 第二条金属线。 滤波器还包括耦合在第一和第三金属线之间的第一电感器和耦合在第二和第三金属线之间的第二电感器。