公开(公告)号：US20220344575A1

公开(公告)日：2022-10-27

申请号：US17241620

申请日：2021-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chiao-Chun Hsu ,  Chung-Yi Yu

IPC: H01L41/273 ,  C23C16/458 ,  C23C16/46 ,  H01L41/297 ,  H01L41/318

Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.

公开(公告)号：US10908494B2

公开(公告)日：2021-02-02

申请号：US15687541

申请日：2017-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Huai-Chih Cheng ,  Hao-Ming Chang ,  Hsao Shih ,  Hsin-Yi Yin

IPC: G03F1/26 ,  G03F1/68 ,  G03F1/76 ,  G03F1/82 ,  G03F7/20

Abstract: A method of manufacturing a photomask includes at least the following steps. First, a phase shift layer and a hard mask layer are formed on a light transmitting substrate. A predetermined mask pattern is split into a first pattern and a second pattern. A series of processes is performed so that the hard mask layer and the phase shift layer have the first pattern and the second pattern. The series of processes includes at least the following steps. First, a first exposure process for transferring the first pattern is performed. Thereafter, a second exposure process for transferring the second pattern is performed. The first exposure process and the second exposure process are executed by different machines.

公开(公告)号：US10896985B2

公开(公告)日：2021-01-19

申请号：US16145585

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/02 ,  H01L31/0352 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US10459332B2

公开(公告)日：2019-10-29

申请号：US15470933

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Ming Chang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Shao-Chi Wei ,  Hsao Shih ,  Li-Chih Lu

IPC: G03F7/26 ,  G03F1/26 ,  H01L21/027 ,  G03F1/38

Abstract: A method of fabricating a photomask includes providing a mask blank; removing a portion of the resist layer to form a patterned resist layer exposing a portion of the cooling layer; patterning the cooling layer by using the patterned resist layer as an etching mask; patterning the opaque layer; and removing the patterned resist layer and the patterned cooling layer. The mask blank includes a light-transmitting substrate and an opaque layer, a cooling layer, and a resist layer sequentially stacked thereon, wherein the cooling layer has a thermal conductivity ranging between 160 and 5000 and an effective atomic number ranging between 5 and 14.

公开(公告)号：US20190244914A1

公开(公告)日：2019-08-08

申请号：US16386630

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/78 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/302 ,  H01L21/306

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.

公开(公告)号：US10276513B2

公开(公告)日：2019-04-30

申请号：US15589195

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/822

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

公开(公告)号：US20180284601A1

公开(公告)日：2018-10-04

申请号：US15470933

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Ming Chang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Shao-Chi Wei ,  Hsao Shih ,  Li-Chih Lu

IPC: G03F1/76 ,  H01L21/027 ,  G03F1/78 ,  G03F1/26 ,  G03F1/50

CPC classification number: G03F1/26 ,  G03F1/38 ,  H01L21/0274

Abstract: A method of fabricating a photomask includes providing a blank mask; removing a portion of the resist layer to form a patterned resist layer exposing a portion of the cooling layer; patterning the cooling layer by using the patterned resist layer as an etching mask; patterning the opaque layer; and removing the patterned resist layer and the patterned cooling layer. The blank mask includes a light-transmitting substrate and an opaque layer, a cooling layer, and a resist layer sequentially stacked thereon, wherein the cooling layer has a thermal conductivity ranging between 160 and 5000 and an effective atomic number ranging between 5 and 14.

公开(公告)号：US09735065B2

公开(公告)日：2017-08-15

申请号：US14656754

申请日：2015-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao Hsu ,  Pei-Cheng Hsu ,  Chia-Ching Huang ,  Chih-Ming Chen ,  Chia-Chen Chen

IPC: G06F17/50 ,  H01L21/66 ,  H01L21/02 ,  G03F1/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L22/12 ,  G03F1/00 ,  G06F17/5068 ,  H01L21/02697 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133

Abstract: A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed.

公开(公告)号：US09209190B2

公开(公告)日：2015-12-08

申请号：US13925984

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L27/10829 ,  H01L24/73 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/91 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.

Abstract translation: 本公开涉及一种形成电容器结构的方法，包括在凹槽的底部和侧壁上沉积由多个氧化物/氮化物/氧化物（ONO）层隔开的多个均匀厚度的多个第一多晶硅（POLY）层，以及 基材表面。 第二POLY层沉积在多个第一POLY层上，被ONO层隔开，并填充凹槽的其余部分。 用第一化学机械抛光（CMP）去除第二POLY层和第二ONO层的部分。 多个第一POLY层和表面上不在电容器结构的掺杂区域内的第一ONO层的一部分用第一图案和蚀刻工艺去除，使得多个第一POLY层中的每一个的顶表面 第一POLY层被暴露以形成接触。

公开(公告)号：US09003337B2

公开(公告)日：2015-04-07

申请号：US13671581

申请日：2012-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Hsu ,  Pei-Cheng Hsu ,  Chia-Ching Huang ,  Chih-Ming Chen ,  Chia-Chen Chen

IPC: G06F17/50 ,  H01L21/02 ,  G03F1/00

CPC classification number: H01L22/12 ,  G03F1/00 ,  G06F17/5068 ,  H01L21/02697 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133

Abstract: A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed.

Abstract translation: 一种在半导体工艺中补偿局部焦点误差的系统和方法。 该方法包括提供掩模版并且在掩模版的第一部分处施加基于与掩模版的第一部分对应的晶片的第一部分的估计局部聚焦误差的台阶高度。 在掩模版上形成多层涂层，并在多层涂层上形成吸收层。 在吸收层上形成光致抗蚀剂。 对光致抗蚀剂进行图案化，对吸收层进行蚀刻并除去残留的光致抗蚀剂。