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    Semiconductor package and manufacturing method thereof
    21.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US10734328B2

    公开(公告)日：2020-08-04

    申请号：US16714793

    申请日：2019-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Ching-Yao Lin ,  Teng-Yuan Lo ,  Chih Wang

    IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/11

    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.

    PACKAGE STRUCTURE, PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    23.
    发明申请
    PACKAGE STRUCTURE, PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190393149A1

    公开(公告)日：2019-12-26

    申请号：US16016664

    申请日：2018-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chuei-Tang Wang ,  Tin-Hao Kuo

    IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

    Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.

    THREE-DIMENSION LARGE SYSTEM INTEGRATION
    27.
    发明申请
    THREE-DIMENSION LARGE SYSTEM INTEGRATION 有权

    公开(公告)号：US20240379637A1

    公开(公告)日：2024-11-14

    申请号：US18777892

    申请日：2024-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Tin-Hao Kuo

    IPC: H01L25/10 ,  H01L25/00 ,  H01L25/18

    Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.

    Integrated circuit package and method
    28.
    发明授权
    Integrated circuit package and method 有权

    公开(公告)号：US12074143B2

    公开(公告)日：2024-08-27

    申请号：US17874598

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/40

    CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/4006

    Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

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