公开(公告)号：US4441938A

公开(公告)日：1984-04-10

申请号：US480158

申请日：1983-03-29

申请人： Richard M. Poliak ,  Dennis L. Rivenburgh ,  Carlos J. Sambucetti

发明人： Richard M. Poliak ,  Dennis L. Rivenburgh ,  Carlos J. Sambucetti

IPC分类号： B23K35/363 ,  B23K35/36 ,  B23K35/34

CPC分类号： B23K35/3612 ,  B23K35/3613

摘要： A soldering flux comprising of rosin, certain acetic acid derivatives, ionic fluorocarbon surfactant, and organic diluent.

摘要翻译： 包含松香，某些乙酸衍生物，离子型氟碳表面活性剂和有机稀释剂的焊剂。

公开(公告)号：US07273803B2

公开(公告)日：2007-09-25

申请号：US10724938

申请日：2003-12-01

申请人： Yu-Ting Cheng ,  Stefanie Ruth Chiras ,  Donald W. Henderson ,  Sung-Kwon Kang ,  Stephen James Kilpatrick ,  Henry A. Nye, III ,  Carlos J. Sambucetti ,  Da-Yuan Shih

发明人： Yu-Ting Cheng ,  Stefanie Ruth Chiras ,  Donald W. Henderson ,  Sung-Kwon Kang ,  Stephen James Kilpatrick ,  Henry A. Nye, III ,  Carlos J. Sambucetti ,  Da-Yuan Shih

IPC分类号： H01L21/44

CPC分类号： B32B15/01 ,  Y10T428/12528 ,  Y10T428/31681

摘要： A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

摘要翻译： 限球冶金包括基板，在基板上形成的阻挡层，形成在阻挡层上的粘合层，形成在粘合层上的第一可焊层，形成在粘合层上的扩散阻挡层，以及第二可焊接 层形成在扩散阻挡层上。

公开(公告)号：US07081680B2

公开(公告)日：2006-07-25

申请号：US10849459

申请日：2004-05-19

申请人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/48 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76886 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05016 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H05K3/244 ,  Y10T29/49117 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/05552

摘要： An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.

摘要翻译： 包括衬底和互连的电结构。 衬底包括在金属层上的导电且耐腐蚀的金属层。 互连电耦合到金属层。 金属层的顶表面位于衬底的顶表面之上，并且金属层的底表面与金属层的顶表面的第一部分直接机械接触。 金属层是非合金的并且包括金属。

公开(公告)号：US06503834B1

公开(公告)日：2003-01-07

申请号：US09677585

申请日：2000-10-03

申请人： Xiaomeng Chen ,  Mahadevaiyer Krishnan ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Soon-Cheon Seo ,  James A. Tornello

发明人： Xiaomeng Chen ,  Mahadevaiyer Krishnan ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Soon-Cheon Seo ,  James A. Tornello

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/288

摘要： The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.

摘要翻译： 本发明提供了增加BEOL互连的可靠性的过程。 该方法包括在晶片衬底上的电介质层上形成导体阵列，抛光上表面，使得导体的表面与电介质层的上表面基本上共面，在上表面上形成合金膜 的导体，并刷清洁导体和电介质层的上表面。

公开(公告)号：US06436803B1

公开(公告)日：2002-08-20

申请号：US09840432

申请日：2001-04-23

申请人： Anilkumar Chinuprasad Bhatt ,  Roy Harvey Magnuson ,  Thomas Richard Miller ,  Voya Rista Markovich ,  Carlos J. Sambucetti ,  Stephen Leo Tisdale

发明人： Anilkumar Chinuprasad Bhatt ,  Roy Harvey Magnuson ,  Thomas Richard Miller ,  Voya Rista Markovich ,  Carlos J. Sambucetti ,  Stephen Leo Tisdale

IPC分类号： H01L2144

摘要： Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.

公开(公告)号：US06153935A

公开(公告)日：2000-11-28

申请号：US409244

申请日：1999-09-30

申请人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

IPC分类号： H01L21/30 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

摘要翻译： 包含双蚀刻停止/扩散屏障的镶嵌互连。 镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。 还可以存在任选的化学机械抛光 - 停止层。 本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。 优选的导电材料是铜。

公开(公告)号：US4415905A

公开(公告)日：1983-11-15

申请号：US465236

申请日：1983-02-10

申请人： Joseph W. Mitchell ,  Merrill W. Shafer ,  Carlos J. Sambucetti

发明人： Joseph W. Mitchell ,  Merrill W. Shafer ,  Carlos J. Sambucetti

IPC分类号： B41J2/385 ,  B41J2/425 ,  G01D15/06 ,  C25B11/10 ,  C25B11/08

CPC分类号： G01D15/06 ,  B41J2/3855 ,  B41J2/425

摘要： The present invention provides a process for electrolytic printing using an improved electrode. The electrode has a region which is an oxide of a metal from the group of ruthenium, iridium, platinum or an alloy thereof. The oxide region is at the extremity of the electrode which during the printing is in close proximity to the printing medium. This oxide region provides an increase in wear resistance of about two orders of magnitude over non-oxidized electrodes. Method for fabricating the described electrode is also set forth.

摘要翻译： 本发明提供一种使用改进电极的电解印刷方法。 电极具有作为来自钌，铱，铂或其合金的金属的氧化物的区域。 氧化物区域位于电极的末端，在印刷过程中与印刷介质相近。 该氧化物区域在非氧化电极上的耐磨性提高了约两个数量级。 还阐述了制造所述电极的方法。

公开(公告)号：US4371273A

公开(公告)日：1983-02-01

申请号：US225688

申请日：1981-01-16

申请人： Arthur H. Kendall ,  Joseph W. Mitchell ,  Carlos J. Sambucetti

发明人： Arthur H. Kendall ,  Joseph W. Mitchell ,  Carlos J. Sambucetti

IPC分类号： B41J2/425 ,  B41J2/395 ,  B41J3/12 ,  B41J3/20

CPC分类号： B41J2/395 ,  Y10T29/49117

摘要： An electrochromic printhead and a method of construction thereof in which the printhead is fabricated from an array of spaced, precisely positioned, small glass tubes. The array of glass tubes defines an array of cylindrical apertures extending through the printhead to form a printing pattern at a printing surface. Each cylindrical aperture has a conductor therein as an active electrode, which defines one dot of an array or matrix of dots possibly formed by the electrochromic printer. An additional conductor is provided as a reference electrode, such that a voltage may be applied between selected active electrodes and the reference electrode to define a particular printing pattern. Electrode wear is substantially eliminated by applying a coating of rutenium oxide crystals on each active electrode at the printing surface. In one disclosed embodiment, each active electrode is formed by a conductive coating applied along the interior surface of each cylindrical aperture. In a further disclosed embodiment, each active electrode comprises a cylindrical wire positioned within each cylindrical aperture. In yet another embodiment, each active electrode is formed by a conductive filler placed within each cylindrical aperture.

摘要翻译： 一种电致变色打印头及其构造方法，其中打印头由间隔开的精确定位的小玻璃管阵列制成。 玻璃管阵列限定了延伸穿过打印头的圆柱形孔阵列，以在打印表面上形成印刷图案。 每个圆柱形孔在其中具有作为有效电极的导体，其限定可能由电致变色打印机形成的阵列或阵列的一个点。 提供附加导体作为参考电极，使得可以在选定的有源电极和参考电极之间施加电压以限定特定的印刷图案。 通过在印刷表面的每个有源电极上施加氧化钌晶体的涂层，基本上消除了电极的磨损。 在一个公开的实施例中，每个有源电极由沿着每个圆柱形孔的内表面施加的导电涂层形成。 在进一步公开的实施例中，每个有源电极包括位于每个圆柱形孔内的圆柱形线。 在另一个实施例中，每个有源电极由放置在每个圆柱形孔内的导电填料形成。

公开(公告)号：US4264693A

公开(公告)日：1981-04-28

申请号：US974640

申请日：1978-12-29

申请人： Barbara A. Gardineer ,  Carlos J. Sambucetti ,  Hugo K. Seitz

发明人： Barbara A. Gardineer ,  Carlos J. Sambucetti ,  Hugo K. Seitz

IPC分类号： B41M5/20 ,  G03C1/725 ,  G03G5/00 ,  G03G17/00

CPC分类号： B41M5/20 ,  G03C1/725 ,  G03C1/7253 ,  G03C1/7256 ,  Y10S428/913 ,  Y10T428/256 ,  Y10T428/31996

摘要： Films are disclosed which are constituted essentially of iodides of heavy metals to which catalysts or sensitizing agents are added to make the films highly sensitive to light and current at room temperature, thus increasing the speed of writing and erasing cycles. The disclosure provides for producing and erasing images on such light and current sensitive films prepared on substrates such as ordinary paper or transparent non-reactive materials. Marking on the films is achieved by light e.g., laser beam and Xenon lamp, or electrical current. Exemplary erasing is done by application of heat. Several examples are disclosed of the formation of these films adherently on non-reactive surfaces.

摘要翻译： 公开了基本上由重金属的碘化物构成的膜，其中加入催化剂或增感剂以使膜在室温下对光和电流高度敏感，从而增加写入和擦除循环的速度。 本公开提供了在诸如普通纸或透明非反应性材料的基底上制备的这种光和电流敏感膜上产生和擦除图像。 膜上的标记通过光例如激光束和氙灯或电流来实现。 通过施加热来进行示例性擦除。 公开了在非反应性表面上粘附形成这些膜的几个实例。

公开(公告)号：US06779711B2

公开(公告)日：2004-08-24

申请号：US10180777

申请日：2002-06-25

申请人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

IPC分类号： B23K120

CPC分类号： H01L24/48 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76886 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05016 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H05K3/244 ,  Y10T29/49117 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/05552

摘要： A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.

摘要翻译： 用于在衬底上制造耐腐蚀导电焊盘的自对准工艺，以及包括允许端子与焊盘连接的互连的结构。 该工艺在初始暴露的金属层上产生金属层。 金属层具有导电性和耐腐蚀性。 该方法包括提供具有暴露表面的金属层的基底，在暴露表面上沉积第二金属层，退火基底以合金包含暴露表面的金属层的一部分和第二金属层的一部分， 以及去除所述第二金属层的非合金部分。 替代方法包括在基底上提供金属层，以及在金属层上无电镀镀耐腐蚀金属或合金。 替代方法可以另外包括在抗腐蚀金属或合金上无电镀第二耐腐蚀金属。