公开(公告)号：US06457234B1

公开(公告)日：2002-10-01

申请号：US09311973

申请日：1999-05-14

申请人： Daniel C. Edelstein ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Anthony K. Stamper

IPC分类号： H01R900

CPC分类号： H01L24/48 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76886 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05016 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H05K3/244 ,  Y10T29/49117 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/05552

摘要： A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.

摘要翻译： 用于在衬底上制造耐腐蚀导电焊盘的自对准（即，空间选择性）工艺以及包括允许端子连接到导电焊盘的互连的相关结构（例如，芯片到封装的连接 ）。 导电焊盘可以包括诸如铜，铝或钨的金属。 自对准工艺在初始暴露的金属层上产生金属层，其中金属层是导电的和耐腐蚀的。 该方法可以通过提供具有暴露表面的金属层的基底，在暴露的表面上沉积第二金属层，退火基底以使包含暴露表面的金属层的一部分和第二金属层的一部分 金属层，并且去除第二金属层的非合金部分。

公开(公告)号：US06779711B2

公开(公告)日：2004-08-24

申请号：US10180777

申请日：2002-06-25

申请人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

IPC分类号： B23K120

CPC分类号： H01L24/48 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76886 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05016 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H05K3/244 ,  Y10T29/49117 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/05552

摘要： A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.

摘要翻译： 用于在衬底上制造耐腐蚀导电焊盘的自对准工艺，以及包括允许端子与焊盘连接的互连的结构。 该工艺在初始暴露的金属层上产生金属层。 金属层具有导电性和耐腐蚀性。 该方法包括提供具有暴露表面的金属层的基底，在暴露表面上沉积第二金属层，退火基底以合金包含暴露表面的金属层的一部分和第二金属层的一部分， 以及去除所述第二金属层的非合金部分。 替代方法包括在基底上提供金属层，以及在金属层上无电镀镀耐腐蚀金属或合金。 替代方法可以另外包括在抗腐蚀金属或合金上无电镀第二耐腐蚀金属。

公开(公告)号：US07081680B2

公开(公告)日：2006-07-25

申请号：US10849459

申请日：2004-05-19

申请人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Anthony K. Stamper ,  Judith M. Rubino ,  Carlos J. Sambucetti

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/48 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76886 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05016 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H05K3/244 ,  Y10T29/49117 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/05552

摘要： An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.

摘要翻译： 包括衬底和互连的电结构。 衬底包括在金属层上的导电且耐腐蚀的金属层。 互连电耦合到金属层。 金属层的顶表面位于衬底的顶表面之上，并且金属层的底表面与金属层的顶表面的第一部分直接机械接触。 金属层是非合金的并且包括金属。

公开(公告)号：US07468320B2

公开(公告)日：2008-12-23

申请号：US11183773

申请日：2005-07-19

申请人： Chao-Kun Hu ,  Robert Rosenberg ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Anthony K. Stamper

发明人： Chao-Kun Hu ,  Robert Rosenberg ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Anthony K. Stamper

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76864 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

摘要翻译： 本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。 该涂层足够薄，以便消除对通过抛光进行附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已经被本发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热 压力消除。 此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。 自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。 提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。 尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US07804391B2

公开(公告)日：2010-09-28

申请号：US11758746

申请日：2007-06-06

申请人： Arne W. Ballantine ,  Cyril Cabral, Jr. ,  Daniel C. Edelstein ,  Anthony K. Stamper

发明人： Arne W. Ballantine ,  Cyril Cabral, Jr. ,  Daniel C. Edelstein ,  Anthony K. Stamper

IPC分类号： H01C10/00

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/242 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49105

摘要： An electrical structure. The electrical structure includes a resistor having a length L and an electrical resistance R(t) at a time t; and a laser radiation directed onto a portion of the resistor, wherein the portion of the resistor includes a fraction F of the length L, wherein the laser radiation heats the portion of the resistor such that the electrical resistance R(t) instantaneously changes at a rate dR/dt, and wherein the resistor is coupled to a semiconductor substrate.

摘要翻译： 电气结构。 电气结构包括在时间t具有长度L和电阻R（t）的电阻器; 以及引导到电阻器的一部分的激光辐射，其中电阻器的该部分包括长度为L的分数F，其中激光辐射加热电阻器的部分，使得电阻R（t）瞬时地在 速率dR / dt，并且其中所述电阻器耦合到半导体衬底。

公开(公告)号：US07585722B2

公开(公告)日：2009-09-08

申请号：US11306746

申请日：2006-01-10

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

公开(公告)号：US20090032959A1

公开(公告)日：2009-02-05

申请号：US11831236

申请日：2007-07-31

申请人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

发明人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

摘要翻译： 提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。 包括导体或半导体的导电结构形成在半导体衬底上。 在导电结构上形成至少一个绝缘体层。 在所述至少一个绝缘体层中形成凹陷区域。 将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。 第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。 具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。 形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

公开(公告)号：US20080173976A1

公开(公告)日：2008-07-24

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US20080132027A1

公开(公告)日：2008-06-05

申请号：US11954782

申请日：2007-12-12

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。