公开(公告)号：US09419050B2

公开(公告)日：2016-08-16

申请号：US14703796

申请日：2015-05-04

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Yung-Tai Tsai ,  Tsang-Yu Liu

IPC: H01L27/146 ,  H01L21/683 ,  H01L21/67 ,  H01L31/18

CPC classification number: H01L27/14687 ,  H01L21/67092 ,  H01L21/6836 ,  H01L27/14685 ,  H01L31/18

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.

Abstract translation: 半导体结构的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 将晶片的第二表面粘附到框架上的紫外线带上，并且移除临时粘合层和载体。 保护带粘附到晶片的第一表面。 使用紫外线照射紫外线带。 切割胶带粘附到保护带和框架上，并且除去紫外线带。 使用第一切割器从晶片的第二表面切割晶片，从而形成芯片之间的多个芯片和多个间隙。 使用宽度小于第一切割器的宽度的第二切割器沿着间隙切割保护带。

公开(公告)号：US09334158B2

公开(公告)日：2016-05-10

申请号：US13900081

申请日：2013-05-22

Applicant: XINTEC INC.

Inventor： Yu-Ting Huang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu

IPC: H01L23/48 ,  B81B7/00 ,  H01L21/64 ,  H01L23/498 ,  H01L23/525 ,  H01L23/00

CPC classification number: B81B7/0077 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/64 ,  H01L23/481 ,  H01L23/498 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，包括：第一半导体衬底; 设置在所述第一半导体衬底上的第二半导体衬底，其中所述第二半导体衬底包括下半导体层，上半导体层和位于所述下半导体层和所述上半导体层之间的绝缘层，以及所述下半导体 层与第一半导体衬底上的至少焊盘电接触; 信号导通结构，设置在所述第一半导体衬底的下表面上，其中所述信号导电结构电连接到所述第一半导体衬底上的信号焊盘; 以及导电层，其设置在所述第二半导体衬底的所述上半导体层上并与所述下半导体层的与所述第一半导体衬底上的所述至少一个焊盘电接触的部分电接触。

公开(公告)号：US09305843B2

公开(公告)日：2016-04-05

申请号：US14596185

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Bing-Siang Chen ,  Chien-Hui Chen ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在所述第一芯片上的第二芯片，其中所述第二芯片的侧表面是化学蚀刻表面; 以及设置在所述第一芯片和所述第二芯片之间的结合体，使得所述第一芯片和所述第二芯片彼此结合。

公开(公告)号：US08552547B2

公开(公告)日：2013-10-08

申请号：US13741320

申请日：2013-01-14

Applicant: Xintec Inc.

Inventor： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC: H01L23/48

CPC classification number: B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract translation: 本发明的实施例提供了一种形成电子器件封装的方法，该方法包括提供具有上表面和相对下表面的载体衬底; 从所述载体基板的上表面形成空腔; 将具有导电电极的电子设备设置在空腔中; 在所述空腔中形成填充层，其中所述填充层围绕所述电子设备; 将载体基板从下表面变薄到预定厚度; 在电子设备或载体衬底中形成至少一个通孔; 以及在所述通孔的侧壁上形成导电层，其中所述导电层与所述导电电极电连接。

公开(公告)号：US20130168784A1

公开(公告)日：2013-07-04

申请号：US13714218

申请日：2012-12-13

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。

公开(公告)号：US11784134B2

公开(公告)日：2023-10-10

申请号：US17140952

申请日：2021-01-04

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6677

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

公开(公告)号：US11319208B2

公开(公告)日：2022-05-03

申请号：US16941465

申请日：2020-07-28

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Chaung-Lin Lai ,  Shu-Ming Chang

IPC: B81C1/00 ,  B81B7/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US10950738B2

公开(公告)日：2021-03-16

申请号：US16512244

申请日：2019-07-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Tsang-Yu Liu

IPC: H01L31/0216 ,  H01L33/62 ,  H01L31/14 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/02

Abstract: A chip package is provided. the chip package includes a substrate having an upper surface, a lower surface, and a sidewall surface that is at an edge of the substrate. The substrate includes a sensing device adjacent to the upper surface of the substrate to sense a light source. The chip package also includes a first color filter layer disposed on the upper surface of the substrate to shield the light source. The first color filter layer includes an opening, so that the first color filter layer surrounds the sensing device via the opening. In addition, the chip package includes a redistribution layer disposed on the lower surface of the substrate. A method of forming the chip package is also provided.

公开(公告)号：US10152180B2

公开(公告)日：2018-12-11

申请号：US15061858

申请日：2016-03-04

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: G06F3/044 ,  H01L21/683 ,  H01L21/768 ,  G06K9/00 ,  H01L23/48 ,  H01L23/31

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.

公开(公告)号：US09947716B2

公开(公告)日：2018-04-17

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chien-Min Lin

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.