公开(公告)号：US09018045B2

公开(公告)日：2015-04-28

申请号：US13942540

申请日：2013-07-15

申请人： Weng Foong Yap ,  Douglas G. Mitchell

发明人： Weng Foong Yap ,  Douglas G. Mitchell

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/181 ,  H01L2924/00

摘要： Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

摘要翻译： 提供了用于制造微电子封装的微电子封装和方法。 在一个实施例中，该方法包括将在其上形成有一个或多个芯再分配层的第一半导体管芯封装在外部成型体中。 外部成型体具有限制芯部再分布层的部分。 在核心再分配层上产生一个或多个顶部再分配层。 接触阵列形成在顶侧再分布层之上，并且通过顶侧再分配层和芯重新分布层电耦合到封装在外部成型体中的第一半导体管芯。

公开(公告)号：US20100276767A1

公开(公告)日：2010-11-04

申请号：US12432377

申请日：2009-04-29

申请人： Lianjun Liu ,  Douglas G. Mitchell

发明人： Lianjun Liu ,  Douglas G. Mitchell

IPC分类号： H01L29/84 ,  H01L21/26

CPC分类号： H04R19/005 ,  H01L29/84 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device.

摘要翻译： 一种器件包括衬底，微电子机械系统（MEMS）结构和电介质膜。 衬底具有第一侧和第二侧，第二侧与第一侧相对。 MEMS结构形成在衬底的第一侧上。 空腔形成在与MEMS结构直接相对的基板中。 空腔具有形成在第二侧上的开口。 电介质膜附着到基片的第二侧并完全覆盖开口。 在一个实施例中，MEMS结构是用于麦克风的隔膜。 另一实施例包括用于形成装置的方法。

公开(公告)号：US06803323B2

公开(公告)日：2004-10-12

申请号：US10159633

申请日：2002-05-30

申请人： Lakshmi Narayan Ramanathan ,  Douglas G. Mitchell ,  Varughese Mathew

发明人： Lakshmi Narayan Ramanathan ,  Douglas G. Mitchell ,  Varughese Mathew

IPC分类号： H01L21302

CPC分类号： H01L28/10 ,  H01L21/32134 ,  H01L27/08

摘要： A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).

摘要翻译： 通过使用过硫酸钠或硝酸铈铵溶液蚀刻复合导电层以去除由复合材料的上部暴露的复合铜层（64）的下部，形成覆盖半导体衬底的无源集成部件（10） 铜层（74,76,78）以暴露下面的表面（62）。

公开(公告)号：US5773359A

公开(公告)日：1998-06-30

申请号：US578255

申请日：1995-12-26

申请人： Douglas G. Mitchell ,  Francis J. Carney ,  Eric J. Woolsey

发明人： Douglas G. Mitchell ,  Francis J. Carney ,  Eric J. Woolsey

IPC分类号： H01L21/60 ,  H01L21/441

CPC分类号： H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19043

摘要： An interconnect system (31) includes an interconnect bump (29) over an under bump metallurgy (25). The under bump metallurgy (25) includes a barrier layer (26) having a barrier material such as titanium, an adhesion layer (28) having an adhesion material such as copper, and a mixture layer (27) having both the barrier material and the adhesion material. The mixture layer (27) is located between the barrier layer (26) and the adhesion layer (28), and the adhesion layer (28) is located between the mixture layer (27) and the interconnect bump (29). The interconnect bump (29) contains solder and is used as an etch mask when patterning the under bump metallurgy (25).

摘要翻译： 互连系统（31）包括在凸块下金属（25）之上的互连凸块（29）。 凸块下冶金（25）包括具有诸如钛的阻挡材料的阻挡层（26），具有诸如铜的粘合材料的粘附层（28）和具有阻挡材料和 粘合材料。 混合层（27）位于阻挡层（26）和粘合层（28）之间，粘合层（28）位于混合层（27）和互连凸块（29）之间。 互连凸块（29）包含焊料，并且当图案化凸块下的金属（25）时用作蚀刻掩模。

公开(公告)号：US5480835A

公开(公告)日：1996-01-02

申请号：US350395

申请日：1994-12-05

申请人： Francis J. Carney ,  George F. Carney ,  Douglas G. Mitchell

发明人： Francis J. Carney ,  George F. Carney ,  Douglas G. Mitchell

IPC分类号： H01L21/60 ,  H05K3/34 ,  H01L21/44

CPC分类号： H01L24/11 ,  H05K3/3452 ,  H05K3/3473 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/2081 ,  H05K2203/043

摘要： A method for forming an electrical interconnect on a substrate. At least one pad (14) is formed on a substrate (11). The pad (14) is formed having a non-wetting surface (12) and a wettable surface (13). Photoresist (44) is patterned on a substrate (41) forming a cavity on a pad (46) leaving a non-wetting surface (42) and a wettable surface (43) exposed. Interconnect material (56) is formed on a non-wetting surface (52) and a wettable surface (53) of pad 57. Interconnect material (56) is reflowed forming an interconnect ball (74) on a wettable surface (73). Surface tension causes interconnect material (56) when reflowed to flow from a non-wetting surface (72) to the wettable surface (73) and ball up to form the interconnect ball (74).

摘要翻译： 一种在基板上形成电互连的方法。 至少一个衬垫（14）形成在衬底（11）上。 衬垫（14）形成为具有非润湿表面（12）和可润湿表面（13）。 光刻胶（44）被图案化在衬底（41）上，在衬垫（46）上形成空腔，留下露出不润湿表面（42）和可润湿表面（43）。 互连材料（56）形成在垫的非润湿表面（52）和可润湿表面（53）上。互连材料（56）被回流，在可润湿表面（73）上形成互连球（74）。 表面张力导致互连材料（56）在回流时从非润湿表面（72）流向可润湿表面（73）并向上球形成互连球（74）。

公开(公告)号：US20110156266A1

公开(公告)日：2011-06-30

申请号：US13043094

申请日：2011-03-08

申请人： Chandrasekaram Ramiah ,  Douglas G. Mitchell ,  Michael F. Petras ,  Paul W. Sanders

发明人： Chandrasekaram Ramiah ,  Douglas G. Mitchell ,  Michael F. Petras ,  Paul W. Sanders

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/82 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/522 ,  H01L23/525 ,  H01L24/24 ,  H01L24/25 ,  H01L24/94 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/94 ,  H01L2924/01018 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/82

摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

摘要翻译： 通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。

公开(公告)号：US06878633B2

公开(公告)日：2005-04-12

申请号：US10329081

申请日：2002-12-23

申请人： Glenn D. Raskin ,  George W. Marlin ,  Douglas G. Mitchell

发明人： Glenn D. Raskin ,  George W. Marlin ,  Douglas G. Mitchell

IPC分类号： H01L21/301 ,  H01L21/311 ,  H01L21/60

CPC分类号： H01L24/05 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2223/6672 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A structure and method for achieving a flip-chip semiconductor device having plated copper inductors (4), transformers (16), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam (8, 24, 28) enables the fabrication of flip-chip solder bumps directly on to inductors and transformers.

摘要翻译： 一种用于实现具有电镀铜电感器（4），变压器（16），互连和功率集成的倒装芯片半导体器件的结构和方法，其电性优良，成本更低，并且提供更高质量的电感器以及更低损耗 片上变压器。 提供焊料坝（8,24,28）可以将倒装芯片焊料凸块直接制造到电感器和变压器上。

公开(公告)号：US06436300B2

公开(公告)日：2002-08-20

申请号：US09124776

申请日：1998-07-30

申请人： Eric J. Woolsey ,  Douglas G. Mitchell ,  George F. Carney ,  Francis J. Carney, Jr. ,  Cary B. Powell

发明人： Eric J. Woolsey ,  Douglas G. Mitchell ,  George F. Carney ,  Francis J. Carney, Jr. ,  Cary B. Powell

IPC分类号： H01B1300

CPC分类号： C23F1/26 ,  H01L21/32134 ,  H01L24/11 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

摘要： A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

公开(公告)号：US06413878B1

公开(公告)日：2002-07-02

申请号：US09546595

申请日：2000-04-10

申请人： Eric J. Woolsey ,  Douglas G. Mitchell ,  George F. Carney ,  Francis J. Carney, Jr. ,  Cary B. Powell

发明人： Eric J. Woolsey ,  Douglas G. Mitchell ,  George F. Carney ,  Francis J. Carney, Jr. ,  Cary B. Powell

IPC分类号： H01L2100

CPC分类号： C23F1/26 ,  H01L21/32134 ,  H01L24/11 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

摘要： A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

摘要翻译： 制造电子部件的方法包括将由焊料组成的顶部金属层（502）设置在由钛或钨构成的底部金属层（201,202）上，并且选择性地蚀刻顶部金属（201,202）上的底部金属层（201,202） 层（502）与由蚀刻剂组成的蚀刻剂混合物（601），用于控制蚀刻剂混合物（601）的温度的添加剂和另外的添加剂以减少顶层（502）的再沉积。

公开(公告)号：US20130207255A1

公开(公告)日：2013-08-15

申请号：US13397034

申请日：2012-02-15

申请人： Alan J. Magnus ,  Carl E.D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

发明人： Alan J. Magnus ,  Carl E.D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

IPC分类号： H01L21/60 ,  H01L23/34 ,  H01L21/56

CPC分类号： H01L23/36 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

摘要翻译： 提供了一种用于形成用于封装在半导体器件封装中的管芯的用于形成用于电和/或热的背面接触的方法和设备。 可以在半导体器件封装内容纳不同厚度的管芯。 本发明的实施例提供耦合到管芯的背面接触的导电基座，其中在将管芯封装在封装内之前执行耦合。 此外，耦合到半导体器件封装内的不同裸片的导电基座具有这样的厚度，使得每个导电基座可以暴露在封装的背面，而不会暴露或损坏任何封装的裸片的背面。 本发明的实施例提供了导电基座由导电或导热材料制成并且使用导电和/或导热粘合剂耦合到器件裸片接触。