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21.发明公开公开(公告)号：US20240332358A1
公开(公告)日：2024-10-03
申请号：US18380711
申请日：2023-10-17
发明人： Seungmin CHA , Jinkyu KIM , Yunsuk NAM
IPC分类号： H01L29/06 , H01L23/48 , H01L27/092 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0673 , H01L23/481 , H01L27/092 , H01L29/0847 , H01L29/41733 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A semiconductor device includes: a first substrate that includes a first region and a second region; an active pattern disposed on the first region; a source/drain pattern disposed on the active pattern; a through contact disposed on the second region; a first metal layer disposed on the through contact; a second substrate disposed on the first metal layer, wherein the second substrate includes an impurity region; a lower bonding pad disposed between the first metal layer and the second substrate; an upper bonding pad disposed on the lower bonding pad; and a power delivery network layer disposed on a bottom surface of the first substrate, wherein the lower bonding pad and the upper bonding pad are in contact with each other, wherein the through contact is connected to the lower bonding pad, and wherein the impurity region is connected to the upper bonding pad.
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公开(公告)号：US20240332335A1
公开(公告)日：2024-10-03
申请号：US18742637
申请日：2024-06-13
发明人： HAJIME YAMAGISHI , KIYOTAKA TABUCHI , MASAKI OKAMOTO , TAKASHI OINOUE , MINORU ISHIDA , SHOTA HIDA , KAZUTAKA YAMANE
IPC分类号： H01L27/146 , H01L23/48 , H01L23/522 , H01L23/528 , H01L23/552 , H01L27/14 , H04N25/616 , H04N25/67 , H04N25/71 , H04N25/75
CPC分类号： H01L27/14634 , H01L23/5225 , H01L23/5286 , H01L23/552 , H01L27/14 , H01L27/146 , H01L27/14623 , H01L27/14636 , H01L27/14643 , H01L23/481 , H01L27/14627 , H04N25/616 , H04N25/67 , H04N25/745 , H04N25/75
摘要： This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
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公开(公告)号：US20240332218A1
公开(公告)日：2024-10-03
申请号：US18741643
申请日：2024-06-12
发明人： Min-Feng KU , Yao-Chun CHUANG , Ching-Pin LIN , Cheng-Chien LI
IPC分类号： H01L23/58 , H01L21/768 , H01L23/00 , H01L23/48
CPC分类号： H01L23/585 , H01L21/76898 , H01L23/481 , H01L23/564
摘要： A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.
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公开(公告)号：US20240332132A1
公开(公告)日：2024-10-03
申请号：US18740523
申请日：2024-06-12
发明人： Jen-Chun Liao , Sung-Yueh Wu , Chien-Ling Hwang , Ching-Hua Hsieh
IPC分类号： H01L23/48 , H01L21/56 , H01L21/768 , H01L23/15 , H01L23/31 , H01L23/498 , H01L23/538
CPC分类号： H01L23/481 , H01L21/56 , H01L21/76898 , H01L23/15 , H01L23/3128 , H01L23/49833 , H01L23/49838 , H01L23/5385 , H01L23/5386
摘要： A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
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公开(公告)号：US20240332100A1
公开(公告)日：2024-10-03
申请号：US18193172
申请日：2023-03-30
申请人： Intel Corporation
发明人： Pratyush Mishra , Marcel Wall , Sashi Kandanur , Pooya Tadayon , Srinivas Pietambaram , Benjamin Duong , Suddhasattwa Nad
IPC分类号： H01L23/15 , H01F27/24 , H01L23/48 , H01L23/498 , H01L23/522
CPC分类号： H01L23/15 , H01F27/24 , H01L23/481 , H01L23/49822 , H01L23/5226
摘要： Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.
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公开(公告)号：US20240332034A1
公开(公告)日：2024-10-03
申请号：US18128601
申请日：2023-03-30
发明人： Shenggao LI
IPC分类号： H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L25/065
CPC分类号： H01L21/565 , H01L23/3121 , H01L23/481 , H01L24/05 , H01L24/16 , H01L24/32 , H01L25/0657 , H01L2224/0401 , H01L2224/05008 , H01L2224/16225 , H01L2224/32225 , H01L2225/06544
摘要： A package structure includes a first integrated circuit (IC) chip, a first set of conductors on the first IC chip, a second set of conductors on the first IC chip, a first redistribution layer coupled to the first set of conductors and the second set of conductors; and a chip layer below the first redistribution layer. The chip layer includes a second IC chip electrically coupled to the first IC chip, a molding material, and a first through-via positioned in the molding material. The first set of conductors is a first set of micro-bumps having a first diameter or a first set of pillars having the first diameter. The second set of conductors is a second set of micro-bumps having a second diameter or a second set of pillars having the second diameter. The second diameter is greater than the first diameter.
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公开(公告)号：US12107076B2
公开(公告)日：2024-10-01
申请号：US17564137
申请日：2021-12-28
发明人： Wonjun Jung , Jasmeet Singh Narang , Tyrone Huang , Christopher Klement , Alan D. Smith , Edward Chang , John Wuu
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L25/0652 , H01L2225/06544
摘要： Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.
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公开(公告)号：US20240324248A1
公开(公告)日：2024-09-26
申请号：US18474179
申请日：2023-09-25
发明人： John Wuu , Kevin Gillespie , Samuel Naffziger , Spence Oliver , Rajit Seahra , Regina T. Schmidt , Raja Swaminathan , Omar Zia
IPC分类号： H10B80/00 , H01L23/544 , H01L25/00 , H01L25/18
CPC分类号： H10B80/00 , H01L23/544 , H01L25/18 , H01L25/50 , H01L23/481 , H01L23/5286 , H01L24/06 , H01L24/08 , H01L2223/54433 , H01L2224/06181 , H01L2224/08145
摘要： A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.
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29.发明公开公开(公告)号：US20240322042A1
公开(公告)日：2024-09-26
申请号：US18672052
申请日：2024-05-23
发明人： CHIH-LIANG CHEN , LEI-CHUN CHOU , JACK LIU , KAM-TOU SIO , HUI-TING YANG , WEI-CHENG LIN , CHUN-HUNG LIOU , JIANN-TYNG TZENG , CHEW-YUEN YOUNG
IPC分类号： H01L29/78 , H01L21/768 , H01L21/8234 , H01L23/48 , H01L23/528 , H01L23/535 , H01L27/088 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/76871 , H01L21/823431 , H01L21/823475 , H01L23/481 , H01L23/528 , H01L23/5286 , H01L23/535 , H01L27/0886 , H01L29/66795 , H01L29/41791
摘要： A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.
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公开(公告)号：US20240321975A1
公开(公告)日：2024-09-26
申请号：US18734477
申请日：2024-06-05
发明人： Kenji SASAKI , Koji INOUE , Shinnosuke TAKAHASHI , Satoshi GOTO , Masao KONDO
IPC分类号： H01L29/417 , H01L23/00 , H01L23/48 , H01L23/528 , H01L27/082 , H01L29/205 , H01L29/737
CPC分类号： H01L29/41708 , H01L23/481 , H01L23/5286 , H01L24/13 , H01L27/0823 , H01L29/205 , H01L29/7371 , H01L2224/13026 , H01L2924/10329 , H01L2924/10338 , H01L2924/13051
摘要： A mesa structure including a collector layer, a base layer, and an emitter layer laminated on a substrate is formed. An emitter electrode electrically connected to the emitter layer is disposed on the mesa structure. Moreover, a base electrode electrically connected to the base layer is disposed on the mesa structure. A collector electrode is disposed in such a manner as to surround the mesa structure in plan view, and the collector electrode is electrically connected to the collector layer. The emitter electrode includes a first part and a second part. In plan view, the base electrode surrounds the first part of the emitter electrode, and the second part of the emitter electrode surrounds the base electrode.
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