公开(公告)号：US20230343744A1

公开(公告)日：2023-10-26

申请号：US18343888

申请日：2023-06-29

申请人： ROHM CO., LTD.

发明人： Akihiro KIMURA ,  Takeshi SUNAGA

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065 ,  H01L23/29 ,  H01L21/52

CPC分类号： H01L24/81 ,  H01L21/568 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/3114 ,  H01L25/0657 ,  H01L24/71 ,  H01L24/90 ,  H01L23/49548 ,  H01L23/293 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L2924/181 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/73265 ,  H01L2924/15174 ,  H01L2224/16225 ,  H01L2224/49171 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2225/06582 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2224/11005 ,  H01L2224/1146 ,  H01L2224/16104 ,  H01L2224/16221 ,  H01L2224/16501

摘要： A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

公开(公告)号：US11791269B2

公开(公告)日：2023-10-17

申请号：US16931690

申请日：2020-07-17

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manepalli

IPC分类号： H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K7/00 ,  H05K7/02 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/52 ,  H01L21/56 ,  H01L21/60 ,  H01L21/84 ,  H01L21/768 ,  H01L23/00 ,  H01L23/02 ,  H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/15 ,  H01L23/18 ,  H01L23/29 ,  H01L23/31 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L23/5383 ,  H01L24/13 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/1579 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

摘要： Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US20230298954A1

公开(公告)日：2023-09-21

申请号：US18325599

申请日：2023-05-30

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Yanhai LIN ,  Mingli HUANG ,  Xiaomin ZHANG ,  An HUANG ,  Guanqiao YANG

IPC分类号： H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L23/053 ,  H01L21/52

CPC分类号： H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L23/053 ,  H01L24/85 ,  H01L21/52 ,  H01L2224/48175 ,  H01L2224/85

摘要： A package structure includes a package substrate. The package structure further includes a printed circuit board on the package substrate. The printed circuit board includes a board body, wherein the board body includes an annular structure, and the annular structure exposes a portion of the package substrate configured to receive a die. The printed circuit board further includes a metal pin on the board body, wherein the metal pin extends beyond the board body in a direction parallel to a top surface of the package substrate, the metal pin is configured to connect to an external circuit, and the metal pin is further configured to connect to the die in response to the die being on the package substrate.

公开(公告)号：US20230266665A1

公开(公告)日：2023-08-24

申请号：US17952687

申请日：2022-09-26

申请人： The University of Manchester

发明人： Scott Lewis ,  Stephen Yeates ,  Richard Winpenny

IPC分类号： G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F1/78 ,  G03F7/038 ,  G03F7/16 ,  G03F7/32 ,  G03F7/40 ,  H01L21/306 ,  H01L21/308 ,  H01L21/52 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00

CPC分类号： G03F7/0044 ,  G03F7/039 ,  G03F7/2059 ,  G03F7/0042 ,  G03F1/78 ,  G03F7/038 ,  G03F7/162 ,  G03F7/168 ,  G03F7/325 ,  G03F7/40 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/52 ,  H01L21/563 ,  H01L21/76838 ,  H01L21/78 ,  H01L24/81 ,  H01L2224/8138

摘要： The present invention relates to a resist composition, especially for use in the production of electronic components via electron beam lithography. In addition to the usual base polymeric component (resist polymer), a secondary electron generator is included in resist compositions of the invention in order to promote secondary electron generation. This unique combination of components increases the exposure sensitivity of resists in a controlled fashion which facilitates the effective production of high-resolution patterned substrates (and consequential electronic components), but at much higher write speeds.

公开(公告)号：US20230246001A1

公开(公告)日：2023-08-03

申请号：US18009920

申请日：2021-09-09

申请人： ROHM CO., LTD.

发明人： Masashi HAYASHIGUCHI ,  Kenichi ONODERA

IPC分类号： H01L25/07 ,  H01L21/52 ,  H01L23/051 ,  H01L23/00

CPC分类号： H01L25/072 ,  H01L21/52 ,  H01L23/051 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/4917 ,  H01L2224/4903

摘要： A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.

公开(公告)号：US20230207402A1

公开(公告)日：2023-06-29

申请号：US18146326

申请日：2022-12-23

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

发明人： Gaius Gillman Fountain, JR. ,  Guilian Gao ,  George Carlton Hudson ,  Laura Wills Mirkarimi

IPC分类号： H01L23/04 ,  H01L21/48 ,  H01L21/52

CPC分类号： H01L23/04 ,  H01L21/486 ,  H01L21/52

摘要： A bonded structure comprises a frame element having a cavity formed through its thickness. The frame element is directly bonded to a first element at a first side and to a second element at a second side enclosing the cavity. The frame element may comprise a through substrate via (TSV). Redundant conductive contact pads may be formed in bonding layers for enhanced direct bonding quality and reliability.

公开(公告)号：US20230207401A1

公开(公告)日：2023-06-29

申请号：US17561396

申请日：2021-12-23

申请人： Micron Technology, Inc.

发明人： Christopher F. Kinney

IPC分类号： H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52

CPC分类号： H01L22/32 ,  H01L23/3157 ,  H01L24/16 ,  H01L21/52 ,  H01L24/81 ,  H01L2224/16227

摘要： Various embodiments described herein provide analog sense points for circuit die, which can form part of an integrated circuit (IC) package and can facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.

公开(公告)号：US20230197638A1

公开(公告)日：2023-06-22

申请号：US17557565

申请日：2021-12-21

申请人： Mohammad Enamul KABIR ,  Keith ZAWADZKI ,  Shakul TANDON ,  Christopher M. PELTO ,  John Kevin TAYLOR ,  Babita DHAYAL

发明人： Mohammad Enamul KABIR ,  Keith ZAWADZKI ,  Shakul TANDON ,  Christopher M. PELTO ,  John Kevin TAYLOR ,  Babita DHAYAL

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/52

CPC分类号： H01L23/564 ,  H01L25/0655 ,  H01L21/52

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques for a barrier that surrounds one or more dies which are electrically coupled with one or more electrical connections on a wafer. The barrier may be a hermetic barrier that is formed on a wafer prior to singulation to prevent moisture intrusion from a side of the wafer that may compromise the one or more electrical connections. Other embodiments may be described and/or claimed.

公开(公告)号：US20230187319A1

公开(公告)日：2023-06-15

申请号：US18076538

申请日：2022-12-07

申请人： Infineon Technologies AG

发明人： Anita Herzer

IPC分类号： H01L23/482 ,  H01L21/56 ,  H01L23/10 ,  H01L21/304 ,  H01L21/52 ,  H01L23/42

CPC分类号： H01L23/4828 ,  H01L21/563 ,  H01L23/10 ,  H01L21/304 ,  H01L21/52 ,  H01L23/42

摘要： A method for fabricating a semiconductor device module includes: providing a substrate having one or more semiconductor dies disposed thereon; providing a housing; applying a reactive tape on partial surfaces of one or both of the substrate and the housing; mounting the housing onto the substrate; filling in a potting material into an interior of the housing; and curing the potting material and the reactive tape.

公开(公告)号：US20230137239A1

公开(公告)日：2023-05-04

申请号：US17970336

申请日：2022-10-20

申请人： STMICROELECTRONICS (GRENOBLE 2) SAS

发明人： Younes BOUTALEB ,  David KAIRE ,  Romain COFFY

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/053 ,  H01L21/52

摘要： The present description concerns an electronic device comprising: an electronic chip comprising an active area on a first surface, and a second surface opposite to the first surface; a substrate, the first surface of said chip being mounted on a third surface of said substrate; and a thermally-conductive cover comprising a transverse portion extending at least above the second surface of said electronic chip, wherein the electronic device further comprises at least one thermally-conductive pillar coupling the second surface of the electronic chip to said transverse portion of said thermally-conductive cover.