公开(公告)号：US09721642B2

公开(公告)日：2017-08-01

申请号：US15155794

申请日：2016-05-16

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US20170207791A1

公开(公告)日：2017-07-20

申请号：US15390362

申请日：2016-12-23

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Barry W. Daly ,  Dustin T. Dunwell ,  Anthony C. Carusone ,  John C. Eble, III

IPC: H03L7/24 ,  H03K3/03 ,  H03K5/156 ,  H03B27/00

CPC classification number: H03L7/24 ,  H03B27/00 ,  H03K3/0315 ,  H03K3/0322 ,  H03K5/133 ,  H03K5/1565

Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

公开(公告)号：US09666250B2

公开(公告)日：2017-05-30

申请号：US15000394

申请日：2016-01-19

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: G06F3/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G11C7/1048 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/16 ,  G06F13/1673 ,  G06F2212/657 ,  G06F2212/68 ,  G11C7/1072 ,  Y02D10/14

Abstract: Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.

公开(公告)号：US09660840B1

公开(公告)日：2017-05-23

申请号：US15209454

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

公开(公告)号：US09660648B2

公开(公告)日：2017-05-23

申请号：US15132532

申请日：2016-04-19

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

公开(公告)号：US09659671B2

公开(公告)日：2017-05-23

申请号：US15192768

申请日：2016-06-24

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US09571231B2

公开(公告)日：2017-02-14

申请号：US14814206

申请日：2015-07-30

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Frederick A. Ware

IPC: H04L1/00 ,  H03M13/15 ,  G06F11/10 ,  H03M13/19

CPC classification number: H04L1/0047 ,  G06F11/1004 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/19

Abstract: A status encoder generates a checksum that encodes a status condition together with the checksum of an associated message. A receiver determines an inverse transformation that when applied to the received status-encoded checksum recovers the parity information associated with the codeword. The status condition can then be recovered based on the selection of the inverse transformation that correctly recovers the parity information from the status-encoded checksum. Beneficially, the status condition can be encoded without requiring additional signal lines or lengthening the codeword relative to conventional error correction devices.

Abstract translation: 状态编码器生成校验和，其将状态条件与相关消息的校验和一起编码。 接收机确定当应用于接收到的状态编码校验和时恢复与码字相关联的奇偶校验信息的逆变换。 然后可以基于从状态编码的校验和正确地恢复奇偶校验信息的逆变换的选择来恢复状态条件。 有利的是，可以编码状态条件，而不需要额外的信号线或相对于传统的纠错装置来延长码字。

公开(公告)号：US09571034B2

公开(公告)日：2017-02-14

申请号：US15049517

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Mohammad Hekmat ,  Farshid Aryanfar ,  Kambiz Kaviani

IPC: H03B27/00 ,  H03B5/12 ,  H01F27/00 ,  H03K5/24 ,  H01F27/28 ,  H03B15/00 ,  H03K5/145 ,  H03K5/00

CPC classification number: H03B27/00 ,  H01F27/006 ,  H01F27/2804 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B15/00 ,  H03K5/145 ,  H03K5/24 ,  H03K2005/00052

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract translation: 耦合多电感及其应用。 一种装置包括几个电路级。 每个电路级包括与其相邻电路级的电感元件重叠的电感元件，形成耦合电路级的回路。 该装置可以是例如具有彼此磁耦合的多个振荡器的多相振荡器，用于在不同相位产生振荡信号。 该装置也可以是例如用于组合输入信号的相位插值器。

公开(公告)号：US09570171B2

公开(公告)日：2017-02-14

申请号：US14866920

申请日：2015-09-26

Applicant: Rambus Inc.

Inventor： Brent Haukness

IPC: G11C13/00 ,  G11C8/08

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/79

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

Abstract translation: 1晶体管1电阻（1T1R）型RRAM单元的存取晶体管的栅极使用电流镜相对于存取晶体管的源极偏置。 在跨过1T1R单元（例如经由位线）施加的电压的影响下，RRAM存储元件从较高的电阻切换到较低的电阻。 当RRAM存储元件从较高的电阻切换到较低电阻时，通过RRAM单元的电流基本上由RRAM器件的较高电阻（而存取晶体管在线性区域中工作）基本确定为基本确定 通过存取晶体管的饱和区工作点。

公开(公告)号：US09570145B2

公开(公告)日：2017-02-14

申请号：US14554904

申请日：2014-11-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/14

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

Abstract translation: 本实施例提供一种支持存储设备中的自刷新操作的系统。 在操作期间，系统将存储器设备从自动刷新状态转变，其中存储器控制器将存储器设备的刷新操作控制到自刷新状态，其中存储器设备控制刷新操作。 当存储器件处于自刷新状态时，系统将刷新操作的进程信息从存储器件发送到存储器控制器。 接下来，当从自刷新状态返回到自动刷新状态时，系统使用从存储装置接收到的进度信息来控制存储器控制器的后续操作的顺序。