公开(公告)号：US20240339136A1

公开(公告)日：2024-10-10

申请号：US18206488

申请日：2023-06-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Kha Nguyen ,  Anh Ly ,  Hieu Van Tran ,  Hien Pham ,  Henry Tran

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/12

Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.

公开(公告)号：US20240312517A1

公开(公告)日：2024-09-19

申请号：US18419079

申请日：2024-01-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G06N3/065 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.

公开(公告)号：US12080355B2

公开(公告)日：2024-09-03

申请号：US17481225

申请日：2021-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0425 ,  G11C16/14 ,  G11C16/3431

Abstract: A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.

公开(公告)号：US20240282369A1

公开(公告)日：2024-08-22

申请号：US18645184

申请日：2024-04-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

公开(公告)号：US20240274591A1

公开(公告)日：2024-08-15

申请号：US18110318

申请日：2023-02-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho KIM ,  CYNTHIA FUNG ,  PARVIZ GHAZAVI ,  JEAN FRANCOIS THIERY ,  CATHERINE DECOBERT ,  GILLES FESTES ,  BRUNO VILLARD ,  YURI TKACHEV ,  XIAN LIU ,  NHAN DO

IPC: H01L27/02 ,  H01L21/38 ,  H01L23/58

CPC classification number: H01L27/0207 ,  H01L21/38 ,  H01L23/585

Abstract: A semiconductor device includes a semiconductor substrate, a first module of circuitry formed on the semiconductor substrate, a second module of circuitry formed on the semiconductor substrate, and a communication ring that encircles the first module of circuitry. The communication ring includes an insulation material disposed over the semiconductor substrate, a plurality of electrical connectors disposed over the semiconductor substrate and extending across a width of the communication ring, and a conductive diffusion in the semiconductor substrate that encircles the first module of circuitry.

公开(公告)号：US12056601B2

公开(公告)日：2024-08-06

申请号：US16830733

申请日：2020-03-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06F1/03 ,  G06F7/78 ,  G06F11/16 ,  G06F17/16 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C29/44

CPC classification number: G06N3/065 ,  G06F1/03 ,  G06F7/78 ,  G06F11/1666 ,  G06F17/16 ,  G11C11/54 ,  G11C11/5635 ,  G11C13/0021 ,  G11C29/44

Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.

公开(公告)号：US11968829B2

公开(公告)日：2024-04-23

申请号：US17834746

申请日：2022-06-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

公开(公告)号：US20240104164A1

公开(公告)日：2024-03-28

申请号：US18080545

申请日：2022-12-13

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  DUC NGUYEN ,  HIEN HO PHAM

IPC: G06F17/16 ,  G06N3/063

CPC classification number: G06F17/16 ,  G06N3/063

Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

公开(公告)号：US20240095509A1

公开(公告)日：2024-03-21

申请号：US18520500

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STANLEY HONG ,  ANH LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC: G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

公开(公告)号：US20240079064A1

公开(公告)日：2024-03-07

申请号：US18139908

申请日：2023-04-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G06N3/065 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/10 ,  G06N3/065 ,  G11C11/5628 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/3459

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.